From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB48A3128A0; Fri, 21 Nov 2025 13:43:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763732612; cv=none; b=UwMkdkMqwZD9ai17zPt1Jj6mKcjxzNvFjoQJQsLtC8bHR29uACfoKxfWdYyOFvXKoHYayNQyF+2ZtDikio5sdpJkUpr2YVDuacIshyOc531lLS7aVsf5PBzmgMcPt+mHVZ2rxzJYxx4dhC51xeeZ2RaH/HjfOip+wJfU2eme4nM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763732612; c=relaxed/simple; bh=Pey6XSnrpcPKIglop5kpgVoMFnTdc2YH3Tr5KZTxm1g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kPH8M2Zef9uhnYV3rhdSNpmRKMrEkMr4IrAoy1eKLazB+6TDnIJhrlC2NVbUH5xwGoUFHKtK6MzzaT6z1g+uaWMh6UWSAv7Ae1AdVjTeMS8o/QBpprUnaRf98/waFO0dVVWbHvLlVNiAxk5dIl50Q7IPX3nlI4tdKvM297+kpp8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=J/goDzHn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="J/goDzHn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 658F9C4CEF1; Fri, 21 Nov 2025 13:43:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1763732612; bh=Pey6XSnrpcPKIglop5kpgVoMFnTdc2YH3Tr5KZTxm1g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J/goDzHnY8ozFfA6XXxAa8HtJyTbOOvzW947OgG+YvTJwQqIBrzmbM4K1S5c3us4+ IuIfnfJtzZJWt+yJcfDty3FSPCVdOt2bE5XSyymkrh++xCABezrbj06w1dRYg/gMb8 PmwMIQfv1EcgVHsbwZPmyr+ULZZPSug53FZwdF9Q= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dmitry Baryshkov , Krzysztof Kozlowski , Sasha Levin Subject: [PATCH 6.6 183/529] drm/msm/dsi/phy_7nm: Fix missing initial VCO rate Date: Fri, 21 Nov 2025 14:08:02 +0100 Message-ID: <20251121130237.528195031@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251121130230.985163914@linuxfoundation.org> References: <20251121130230.985163914@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Krzysztof Kozlowski [ Upstream commit 5ddcb0cb9d10e6e70a68e0cb8f0b8e3a7eb8ccaf ] Driver unconditionally saves current state on first init in dsi_pll_7nm_init(), but does not save the VCO rate, only some of the divider registers. The state is then restored during probe/enable via msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() -> dsi_7nm_pll_restore_state(). Restoring calls dsi_pll_7nm_vco_set_rate() with pll_7nm->vco_current_rate=0, which basically overwrites existing rate of VCO and messes with clock hierarchy, by setting frequency to 0 to clock tree. This makes anyway little sense - VCO rate was not saved, so should not be restored. If PLL was not configured configure it to minimum rate to avoid glitches and configuring entire in clock hierarchy to 0 Hz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/657827/ Link: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-9-ee633e3ddbff@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 47ee2fd569db4..bed9867ced6d4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -797,6 +797,12 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_pll_save_state(phy); + /* + * Store also proper vco_current_rate, because its value will be used in + * dsi_7nm_pll_restore_state(). + */ + if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE)) + pll_7nm->vco_current_rate = pll_7nm->phy->cfg->min_pll_rate; return 0; } -- 2.51.0