From: Greg KH <gregkh@linuxfoundation.org>
To: Avadhut Naik <avadhut.naik@amd.com>
Cc: stable@vger.kernel.org, sashal@kernel.org,
linux-kernel@vger.kernel.org,
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
Tony Luck <tony.luck@intel.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Borislav Petkov <bp@alien8.de>, Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Subject: Re: [PATCH] x86/mce: Handle AMD threshold interrupt storms
Date: Fri, 21 Nov 2025 07:53:55 +0100 [thread overview]
Message-ID: <2025112144-wizard-upcountry-292d@gregkh> (raw)
In-Reply-To: <20251120214139.1721338-1-avadhut.naik@amd.com>
On Thu, Nov 20, 2025 at 09:41:24PM +0000, Avadhut Naik wrote:
> From: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
>
> Extend the logic of handling CMCI storms to AMD threshold interrupts.
>
> Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and
> per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on
> a storm. Rather, disable the interrupt on the corresponding CPU and bank.
> Re-enable back the interrupts if enough consecutive polls of the bank show no
> corrected errors (30, as programmed by Intel).
>
> Turning off the threshold interrupts would be a better solution on AMD systems
> as other error severities will still be handled even if the threshold
> interrupts are disabled.
>
> Also, AMD systems currently allow banks to be managed by both polling and
> interrupts. So don't modify the polling banks set after a storm ends.
>
> [Tony: Small tweak because mce_handle_storm() isn't a pointer now]
> [Yazen: Rebase and simplify]
>
> Stable backport notes:
> 1. Currently, when a Machine check interrupt storm is detected, the bank's
> corresponding bit in mce_poll_banks per-CPU variable is cleared by
> cmci_storm_end(). As a result, on AMD's SMCA systems, errors injected or
> encountered after the storm subsides are not logged since polling on that
> bank has been disabled. Polling banks set on AMD systems should not be
> modified when a storm subsides.
>
> 2. This patch is a snippet from the CMCI storm handling patch (link below)
> that has been accepted into tip for v6.19. While backporting the patch
> would have been the preferred way, the same cannot be undertaken since
> its part of a larger set. As such, this fix will be temporary. When the
> original patch and its set is integrated into stable, this patch should be
> reverted.
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Link: https://lore.kernel.org/20251104-wip-mca-updates-v8-0-66c8eacf67b9@amd.com
> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
> ---
> This is somewhat of a new scenario for me. Not really sure about the
> procedure. Hence, haven't modified the commit message and removed the
> tags. If required, will rework both.
> Also, while this issue can be encountered on AMD systems using v6.8 and
> later stable kernels, we would specifically prefer for this fix to be
> backported to v6.12 since its LTS.
What is the git commit id of this change in Linus's tree?
next prev parent reply other threads:[~2025-11-21 6:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 21:41 [PATCH] x86/mce: Handle AMD threshold interrupt storms Avadhut Naik
2025-11-20 21:43 ` kernel test robot
2025-11-20 21:53 ` Borislav Petkov
2025-11-21 1:59 ` Naik, Avadhut
2025-11-21 6:54 ` Greg KH
2025-11-21 6:53 ` Greg KH [this message]
2025-11-21 7:04 ` Naik, Avadhut
2025-11-21 7:09 ` Greg KH
2025-11-21 9:31 ` Borislav Petkov
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