Re: [PATCH] drm/msm: Fix a7xx per pipe register programming

[kernel test robot <lkp@intel.com>]

Hi Anna,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530]

url:    https://github.com/intel-lab-lkp/linux/commits/Anna-Maniscalco/drm-msm-Fix-a7xx-per-pipe-register-programming/20251127-074833
base:   7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
patch link:    https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0cf616401f%40gmail.com
patch subject: [PATCH] drm/msm: Fix a7xx per pipe register programming
config: loongarch-allmodconfig (https://download.01.org/0day-ci/archive/20251128/202511281253.rIkrIiqt-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251128/202511281253.rIkrIiqt-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511281253.rIkrIiqt-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:984:35: warning: & has lower precedence than ==; == will be evaluated first [-Wparentheses]
     984 |                         if (pipe_reglist->regs[i].pipe & BIT(pipe_id) == 0)
         |                                                        ^~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/msm/adreno/a6xx_gpu.c:984:35: note: place parentheses around the '==' expression to silence this warning
     984 |                         if (pipe_reglist->regs[i].pipe & BIT(pipe_id) == 0)
         |                                                        ^ ~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/msm/adreno/a6xx_gpu.c:984:35: note: place parentheses around the & expression to evaluate it first
     984 |                         if (pipe_reglist->regs[i].pipe & BIT(pipe_id) == 0)
         |                             ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~
   1 warning generated.


vim +984 drivers/gpu/drm/msm/adreno/a6xx_gpu.c

   931	
   932	static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
   933	{
   934		struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
   935		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
   936		const struct adreno_reglist_list *reglist;
   937		const struct adreno_reglist_pipe_list *pipe_reglist;
   938		void *ptr = a6xx_gpu->pwrup_reglist_ptr;
   939		struct cpu_gpu_lock *lock = ptr;
   940		u32 *dest = (u32 *)&lock->regs[0];
   941		u32 pipe_reglist_count = 0;
   942		int i;
   943	
   944		lock->gpu_req = lock->cpu_req = lock->turn = 0;
   945	
   946		reglist = adreno_gpu->info->a6xx->ifpc_reglist;
   947		lock->ifpc_list_len = reglist->count;
   948	
   949		/*
   950		 * For each entry in each of the lists, write the offset and the current
   951		 * register value into the GPU buffer
   952		 */
   953		for (i = 0; i < reglist->count; i++) {
   954			*dest++ = reglist->regs[i];
   955			*dest++ = gpu_read(gpu, reglist->regs[i]);
   956		}
   957	
   958		reglist = adreno_gpu->info->a6xx->pwrup_reglist;
   959		lock->preemption_list_len = reglist->count;
   960	
   961		for (i = 0; i < reglist->count; i++) {
   962			*dest++ = reglist->regs[i];
   963			*dest++ = gpu_read(gpu, reglist->regs[i]);
   964		}
   965	
   966		/*
   967		 * The overall register list is composed of
   968		 * 1. Static IFPC-only registers
   969		 * 2. Static IFPC + preemption registers
   970		 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects)
   971		 *
   972		 * The first two lists are static. Size of these lists are stored as
   973		 * number of pairs in ifpc_list_len and preemption_list_len
   974		 * respectively. With concurrent binning, Some of the perfcounter
   975		 * registers being virtualized, CP needs to know the pipe id to program
   976		 * the aperture inorder to restore the same. Thus, third list is a
   977		 * dynamic list with triplets as
   978		 * (<aperture, shifted 12 bits> <address> <data>), and the length is
   979		 * stored as number for triplets in dynamic_list_len.
   980		 */
   981		pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist;
   982		for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
   983			for (i = 0; i < pipe_reglist->count; i++) {
 > 984				if (pipe_reglist->regs[i].pipe & BIT(pipe_id) == 0)
   985					continue;
   986				*dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);
   987				*dest++ = pipe_reglist->regs[i].offset;
   988				*dest++ = a7xx_read_pipe(gpu, pipe_id,
   989							 pipe_reglist->regs[i].offset);
   990				pipe_reglist_count++;
   991			}
   992		}
   993		lock->dynamic_list_len = pipe_reglist_count;
   994	}
   995	

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