From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3335631ED8D; Wed, 3 Dec 2025 15:54:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764777248; cv=none; b=ai+WEFI8Mmsbm3rbyNT89RPla0rPK7pWEMqh4JXRn0OtfBtGmuVqDTLqVAyA/FROTPJu6/t4o2oy4E9Cw5JevFFiDuY7upkIpqcTyyq8r5kI45KS58qUyudJ0wObLBDrqY1vofGyfcxVHhkT2+9STbHBHSIYDQCPMSYXAQHuGN8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764777248; c=relaxed/simple; bh=dfPx3cIQEFqlR4iRW5NvppB6Ff2CWkYi9kBXcWgz1Hk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z8Z/G3YdQasUTe2K2kjce3TTr6nBZblpmHPcpPLAkOy/pjpONWJ5EwDlXwIvwMvExCNXEn/E21oW1kFoh7RWvsAKGuPKBq2+AzL/MJBuKCR4iHySl7/K+Knj38zeUq0dZRI3oxjkhwezsnrLffyNL56NUKarTGcKq/dtVw2e3Oo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=dVbXQa9N; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="dVbXQa9N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65A23C2BCB9; Wed, 3 Dec 2025 15:54:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1764777247; bh=dfPx3cIQEFqlR4iRW5NvppB6Ff2CWkYi9kBXcWgz1Hk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dVbXQa9NpIT0ev1DG1+DaKeb2epNyWR5L50YFXn0fhDOtfW1TyIRgG3SxMmkkbuve QVdP59xCd5pzwoE8r6nTbpoRjnpr9rLHXuTNnfT5HEDKKjhHoPD9cQTsyI/rxKkBFY W8rkDwd78Z+K/QO+zeDY6b67byyBB3QpwqUu/mpo= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , =?UTF-8?q?Jouni=20H=C3=B6gander?= , Rodrigo Vivi Subject: [PATCH 6.17 127/146] drm/i915/psr: Reject async flips when selective fetch is enabled Date: Wed, 3 Dec 2025 16:28:25 +0100 Message-ID: <20251203152351.108995964@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251203152346.456176474@linuxfoundation.org> References: <20251203152346.456176474@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.17-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ville Syrjälä commit 7c373b3bd03c77fe8f6ea206ed49375eb4d43d13 upstream. The selective fetch code doesn't handle asycn flips correctly. There is a nonsense check for async flips in intel_psr2_sel_fetch_config_valid() but that only gets called for modesets/fastsets and thus does nothing for async flips. Currently intel_async_flip_check_hw() is very unhappy as the selective fetch code pulls in planes that are not even async flips capable. Reject async flips when selective fetch is enabled, until someone fixes this properly (ie. disable selective fetch while async flips are being issued). Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20251105171015.22234-1-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander (cherry picked from commit a5f0cc8e0cd4007370af6985cb152001310cf20c) Signed-off-by: Rodrigo Vivi Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_psr.c | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5958,6 +5958,14 @@ static int intel_async_flip_check_uapi(s return -EINVAL; } + /* FIXME: selective fetch should be disabled for async flips */ + if (new_crtc_state->enable_psr2_sel_fetch) { + drm_dbg_kms(display->drm, + "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n", + crtc->base.base.id, crtc->base.name); + return -EINVAL; + } + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { if (plane->pipe != crtc->pipe) --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1274,12 +1274,6 @@ static bool intel_psr2_sel_fetch_config_ return false; } - if (crtc_state->uapi.async_flip) { - drm_dbg_kms(display->drm, - "PSR2 sel fetch not enabled, async flip enabled\n"); - return false; - } - return crtc_state->enable_psr2_sel_fetch = true; }