From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA35335571 for ; Mon, 5 Jan 2026 16:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767631744; cv=none; b=hQGcd+aooXZVl8TPPFJByxk1ajqd22QYjNTXgQ3FSFnzaALUskzqC/yIrbsRMWNeFCC8z5U78dwYqxD/TIaw0nhrWmLKhZnHE3qcav6r7cp/8hKk5zprMwh24QN7aFHLZru3/6y2kMun/yPQi9sy+0kk7qJU4vYGjZ2k+WGRkRY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767631744; c=relaxed/simple; bh=Vly797Yif5Uemi39W9M0qyPyjRdh1H5ro1LHScvao1o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vbr2RTkwq1/puxp+LzIfCq4jYjQqxM+qh5gKOlbXSbjx7E+csFyyxELfv4/I9EznpSTUbtj2T0cVeLHYkL+X4nr/n8AhG4MAsqrRdZsBJP3svs98vXif7Gj3Ct4cCMCvPPtYJRbUGTz84p/3jmR7f3WZ5jflww4XFWGJSWX13jU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sSV6Wn3G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sSV6Wn3G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 234D4C116D0; Mon, 5 Jan 2026 16:49:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767631744; bh=Vly797Yif5Uemi39W9M0qyPyjRdh1H5ro1LHScvao1o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sSV6Wn3G8FSWFlDyxBEFVoyxlLiIpthnuRa5JzkNBtsCQe6/sraoxtIuXEaAsCo2M 9FOp56Y7avX2miEmhpYTUXbNV3Cf1a3mesVrfq/YgG3/ifO+5j7mAglVnGLFIs/EST a36TxeHYxcwlBwYb70nJNkWGK4B55OWSF5zxap2FyhUduBLLrHkCoARgFAJOKCqZNE uvj700NrTYe5z3AZksoK3pBFD8qZMt8s2k20JaGXC8c6G+PLhVmXSer5JjJnKHJi90 vabDnYj94uZJcvqCQibAl+u7fsNlxqc7l3NLOEd0dSjfhJGB2HhPcUH2Kn1Ix7lFOO /V0IDzfj9VxwQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Benjamin Gaignard , Andrzej Pietrasiewicz , Ezequiel Garcia , Philipp Zabel , Hans Verkuil , Mauro Carvalho Chehab , Sasha Levin Subject: [PATCH 6.6.y 2/3] media: verisilicon: g2: Use common helpers to compute chroma and mv offsets Date: Mon, 5 Jan 2026 11:48:59 -0500 Message-ID: <20260105164900.2676927-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260105164900.2676927-1-sashal@kernel.org> References: <2026010507-cringe-sterile-73c8@gregkh> <20260105164900.2676927-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Benjamin Gaignard [ Upstream commit 3eeaee737dcee3c32e256870dbc2687a2a6fe970 ] HEVC and VP9 are running on the same hardware and share the same chroma and motion vectors offset constraint. Create common helpers functions for these computation. Source and destination buffer height may not be the same because alignment constraint are different so use destination height to compute chroma offset because we target this buffer as hardware output. To be able to use the helpers in both VP9 HEVC code remove dec_params and use context->bit_depth instead. Signed-off-by: Benjamin Gaignard Reviewed-by: Andrzej Pietrasiewicz CC: Ezequiel Garcia CC: Philipp Zabel Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: 19c286b75507 ("media: verisilicon: Fix CPU stalls on G2 bus error") Signed-off-by: Sasha Levin --- .../media/platform/verisilicon/hantro_g2.c | 14 ++++++++++ .../platform/verisilicon/hantro_g2_hevc_dec.c | 18 ++----------- .../platform/verisilicon/hantro_g2_vp9_dec.c | 26 +++---------------- .../media/platform/verisilicon/hantro_hw.h | 3 +++ 4 files changed, 23 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_g2.c b/drivers/media/platform/verisilicon/hantro_g2.c index ee5f14c5f8f2..b880a6849d58 100644 --- a/drivers/media/platform/verisilicon/hantro_g2.c +++ b/drivers/media/platform/verisilicon/hantro_g2.c @@ -8,6 +8,8 @@ #include "hantro_hw.h" #include "hantro_g2_regs.h" +#define G2_ALIGN 16 + void hantro_g2_check_idle(struct hantro_dev *vpu) { int i; @@ -42,3 +44,15 @@ irqreturn_t hantro_g2_irq(int irq, void *dev_id) return IRQ_HANDLED; } + +size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx) +{ + return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; +} + +size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx) +{ + size_t cr_offset = hantro_g2_chroma_offset(ctx); + + return ALIGN((cr_offset * 3) / 2, G2_ALIGN); +} diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c index d1971af5f7fa..78eb52edd5c3 100644 --- a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c +++ b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c @@ -8,20 +8,6 @@ #include "hantro_hw.h" #include "hantro_g2_regs.h" -#define G2_ALIGN 16 - -static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx) -{ - return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; -} - -static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx) -{ - size_t cr_offset = hantro_hevc_chroma_offset(ctx); - - return ALIGN((cr_offset * 3) / 2, G2_ALIGN); -} - static void prepare_tile_info_buffer(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; @@ -384,8 +370,8 @@ static int set_ref(struct hantro_ctx *ctx) struct hantro_dev *vpu = ctx->dev; struct vb2_v4l2_buffer *vb2_dst; struct hantro_decoded_buffer *dst; - size_t cr_offset = hantro_hevc_chroma_offset(ctx); - size_t mv_offset = hantro_hevc_motion_vectors_offset(ctx); + size_t cr_offset = hantro_g2_chroma_offset(ctx); + size_t mv_offset = hantro_g2_motion_vectors_offset(ctx); u32 max_ref_frames; u16 dpb_longterm_e; static const struct hantro_reg cur_poc[] = { diff --git a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c index 6db1c32fce4d..342e543dee4c 100644 --- a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c +++ b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c @@ -16,8 +16,6 @@ #include "hantro_vp9.h" #include "hantro_g2_regs.h" -#define G2_ALIGN 16 - enum hantro_ref_frames { INTRA_FRAME = 0, LAST_FRAME = 1, @@ -90,22 +88,6 @@ static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_ return 0; } -static size_t chroma_offset(const struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp9_frame *dec_params) -{ - int bytes_per_pixel = dec_params->bit_depth == 8 ? 1 : 2; - - return ctx->src_fmt.width * ctx->src_fmt.height * bytes_per_pixel; -} - -static size_t mv_offset(const struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp9_frame *dec_params) -{ - size_t cr_offset = chroma_offset(ctx, dec_params); - - return ALIGN((cr_offset * 3) / 2, G2_ALIGN); -} - static struct hantro_decoded_buffer * get_ref_buf(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) { @@ -156,13 +138,13 @@ static void config_output(struct hantro_ctx *ctx, luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); + chroma_addr = luma_addr + hantro_g2_chroma_offset(ctx); hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr); - dst->vp9.chroma_offset = chroma_offset(ctx, dec_params); + dst->vp9.chroma_offset = hantro_g2_chroma_offset(ctx); - mv_addr = luma_addr + mv_offset(ctx, dec_params); + mv_addr = luma_addr + hantro_g2_motion_vectors_offset(ctx); hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr); - dst->vp9.mv_offset = mv_offset(ctx, dec_params); + dst->vp9.mv_offset = hantro_g2_motion_vectors_offset(ctx); } struct hantro_vp9_ref_reg { diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index 7f33f7b07ce4..c7a2a20c70b7 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -519,6 +519,9 @@ hantro_av1_mv_size(unsigned int width, unsigned int height) return ALIGN(num_sbs * 384, 16) * 2 + 512; } +size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx); +size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx); + int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); void hantro_mpeg2_dec_copy_qtable(u8 *qtable, -- 2.51.0