From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E84308F1D; Wed, 28 Jan 2026 15:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769615299; cv=none; b=sjBG50TZY4tXwiVZeE7+IhRkFFZ/tuH7s4sfOycSU3zYzc0Ropo61qvS3U0f8hu0j3pb/q77qiXsudAZk/zzXsmAno1W7RL0m6JpfaTy+Rbay7o6BWb6pxIPUV8/3XXa58vijP/kfttlfcCX2wwCsoKQQkY74aIFffGQcFQhgDI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769615299; c=relaxed/simple; bh=1sEumzKNBDl9k/ek/iePFiALEqIKtp0rAwkcDKllBEo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KhlVwIct/nTUygBTKtRMJMazFeTU2LlqMi38s+b1KfRvuUJx0c13HMOqHWY+pxUtO3dWr4HLEw012rhHOxAUIgIzn/3The6FTaG4/m5kIL04UKBRFj7zcRUNoGY8Pe+BBCvYh876cjApTcm0Kh2uXkFrA8ebzQWmxHnHFJ1lS2U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=JTF/MSee; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="JTF/MSee" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 179CAC4CEF1; Wed, 28 Jan 2026 15:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1769615299; bh=1sEumzKNBDl9k/ek/iePFiALEqIKtp0rAwkcDKllBEo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JTF/MSeeZ0mFAbGqwgYr29fTeRiWtznpjskLyin+XWZ4dcRVSd1PHsUSP9x4Izu7x ozlP/DCaPCb7h6FX/jSt/i5xtBlKJH89qrbSzbN0axhD6hZ3aUzbDVRadsOxAI2Z5r XlcNy+QXICr7OY+unPWfqRTked3Pbxz9iqi/1Vlw= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, "=?UTF-8?q?Jan=20H . =20Sch=C3=B6nherr?=" , Peter Zijlstra , Fernand Sieber Subject: [PATCH 6.12 137/169] perf/x86/intel: Do not enable BTS for guests Date: Wed, 28 Jan 2026 16:23:40 +0100 Message-ID: <20260128145338.938017302@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128145334.006287341@linuxfoundation.org> References: <20260128145334.006287341@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Fernand Sieber commit 91dcfae0ff2b9b9ab03c1ec95babaceefbffb9f4 upstream. By default when users program perf to sample branch instructions (PERF_COUNT_HW_BRANCH_INSTRUCTIONS) with a sample period of 1, perf interprets this as a special case and enables BTS (Branch Trace Store) as an optimization to avoid taking an interrupt on every branch. Since BTS doesn't virtualize, this optimization doesn't make sense when the request originates from a guest. Add an additional check that prevents this optimization for virtualized events (exclude_host). Reported-by: Jan H. Schönherr Suggested-by: Peter Zijlstra Signed-off-by: Fernand Sieber Signed-off-by: Peter Zijlstra (Intel) Cc: Link: https://patch.msgid.link/20251211183604.868641-1-sieberf@amazon.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/perf_event.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1513,13 +1513,22 @@ static inline bool intel_pmu_has_bts_per struct hw_perf_event *hwc = &event->hw; unsigned int hw_event, bts_event; - if (event->attr.freq) + /* + * Only use BTS for fixed rate period==1 events. + */ + if (event->attr.freq || period != 1) + return false; + + /* + * BTS doesn't virtualize. + */ + if (event->attr.exclude_host) return false; hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); - return hw_event == bts_event && period == 1; + return hw_event == bts_event; } static inline bool intel_pmu_has_bts(struct perf_event *event)