From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 699E72D6E63; Wed, 28 Jan 2026 15:37:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769614632; cv=none; b=ErP3luq7PguEjNAHzFUOK1YPT5dCms9V/loYDZkklvc/he9gm60ZYos2x1p7N7UBPpztmHe3HzQU0jvlDnUO7v1UpTLZ/PSiG0TTfYOOnxd0GVUSHDHnIeC2xW8ELVjUTz7G7Ic1/RRzSLUpVo6pCjU5sV/TCoHvCfdkbiiVHko= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769614632; c=relaxed/simple; bh=9hz7TB5XRHtIdJsDPosMmTwjJeimxfLq6j2YqRu0HKc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QHkyYTH7J/J1MhUMm+oA4UKjAixFXBaEQAIv8QFWw/LME+XSv5pySCNwlO81Gal+LRNdinAhf7SJyS9wYwLdikiuhdWKKDFEOK6wXYEg77nLYcOAUAQXbz6mYwpTnZ/dks+R+xXSf+dIhEPNHUdl7eh7H75mp9gAA6h53BBFYgU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=cnAycEBR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="cnAycEBR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A9CFC4CEF1; Wed, 28 Jan 2026 15:37:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1769614632; bh=9hz7TB5XRHtIdJsDPosMmTwjJeimxfLq6j2YqRu0HKc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cnAycEBRsaV/unoyeOAKkD4Kuyn/KO0f4f2xRc0jjC4yc0ZEETm7HNJD7v14F6TrA T3VfZyGvAvl9mv6rXNIzYHxr7MyjUZ8W53jmuEAh5SHaEQqnC+Gz3+4/4+xQP87wdm s59x9ZA8o9n7URbZC24rkx8BLOfk/VGuQR6dA/gg= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Sebastian Reichel , Yifeng Zhao , Shawn Lin , Ulf Hansson Subject: [PATCH 6.6 195/254] mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode Date: Wed, 28 Jan 2026 16:22:51 +0100 Message-ID: <20260128145351.815107250@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128145344.698118637@linuxfoundation.org> References: <20260128145344.698118637@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shawn Lin commit 3009738a855cf938bbfc9078bec725031ae623a4 upstream. When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller requires maintaining a minimum clock of 52MHz in these modes. Add a check to prevent illegal clock reduction through debugfs: root@debian:/# echo 50000000 > /sys/kernel/debug/mmc0/clock root@debian:/# [ 30.090146] mmc0: running CQE recovery mmc0: cqhci: Failed to halt mmc0: cqhci: spurious TCN for tag 0 WARNING: drivers/mmc/host/cqhci-core.c:797 at cqhci_irq+0x254/0x818, CPU#1: kworker/1:0H/24 Modules linked in: CPU: 1 UID: 0 PID: 24 Comm: kworker/1:0H Not tainted 6.19.0-rc1-00001-g09db0998649d-dirty #204 PREEMPT Hardware name: Rockchip RK3588 EVB1 V10 Board (DT) Workqueue: kblockd blk_mq_run_work_fn pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : cqhci_irq+0x254/0x818 lr : cqhci_irq+0x254/0x818 ... Fixes: c6f361cba51c ("mmc: sdhci-of-dwcmshc: add support for rk3588") Cc: Sebastian Reichel Cc: Yifeng Zhao Signed-off-by: Shawn Lin Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/sdhci-of-dwcmshc.c | 7 +++++++ 1 file changed, 7 insertions(+) --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -244,6 +244,13 @@ static void dwcmshc_rk3568_set_clock(str sdhci_writel(host, extra, reg); if (clock <= 52000000) { + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || + host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { + dev_err(mmc_dev(host->mmc), + "Can't reduce the clock below 52MHz in HS200/HS400 mode"); + return; + } + /* * Disable DLL and reset both of sample and drive clock. * The bypass bit and start bit need to be set if DLL is not locked.