From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82ACD2C0F8C for ; Wed, 28 Jan 2026 18:26:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624777; cv=none; b=Bcha0eMv+rPoAjDQwltr3aDhRuZuzQtgBvenJwCi/QloHdgRwECp9A3HrVVJrV1AXEUbtJ7eejXoPgHv1cQ6kqP/Ew1GLKOGLLgFh19enFf1YOBT+BN3xfei6+nJB7z5zvOJpY+BzAZXnKRA2jY3LaQoAjckVAps802aVZG6dJQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624777; c=relaxed/simple; bh=AwlUMITnq/8APJ54MfXtAP4ujHSaF4vaUD8teVnjXko=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fizD7ektOvpFICdobWIZZKra8q3CfHBeHFqsL+nzktgyYP9hJS4t/4/+8r1PVWNCxzHVNZ4tnBTG7vnj3QPqAPTbNa6Ou1YlBZ7wg6Xw94Dzpzuc/Lka8SZCi7zok46UeUvXyR+sVJjc9grnQmW0n4mPAjhKQrrrcg1qbJ4KeSU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n4HbabS6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n4HbabS6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92A8FC4CEF1; Wed, 28 Jan 2026 18:26:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769624777; bh=AwlUMITnq/8APJ54MfXtAP4ujHSaF4vaUD8teVnjXko=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n4HbabS6Wd+cI4scTDmDKBnU3m4kRW+14rcIVT9/eMIJ8j0DLzh/GuG+RUhfU3wv/ BsodArPxuqkCgFmvFr8IqOW90k3nBdEz4LEvNYJkY5CQjQH4UPayR6L/NSeheurNvR B8Xf+dVHHEaWMWsBPQsUPXGMMxi1acbWVqNSj1F3iew/Rbch1jRvfGr9KAiW8AhRu4 cmnO9Q2aku9mJhJd5dm8l1l9FdMZSkM3QgbMllsX0ZhgcogXZTIXLgIe6TzYpm/1HG I48Q4WW6Tf8Z9/bbNtnyJGYc4jxk6WxWkztFY4/HLTGwVLZxBpskoTJb9pvwPCH0qP zCUAYPCjk4Nsw== From: Sasha Levin To: stable@vger.kernel.org Cc: Shawn Lin , Ulf Hansson , Sasha Levin Subject: [PATCH 6.1.y 1/2] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for rockchip platform Date: Wed, 28 Jan 2026 13:26:14 -0500 Message-ID: <20260128182615.2660161-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2026012749-barrier-oppressor-3ac6@gregkh> References: <2026012749-barrier-oppressor-3ac6@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Shawn Lin [ Upstream commit b75a52b0dda353aeefb4830a320589a363f49579 ] For Rockchip platform, DLL bypass bit and start bit need to be set if DLL is not locked. And adjust pre-change delay to 0x3 for better signal test result. Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Ulf Hansson Stable-dep-of: 3009738a855c ("mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode") Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index b07c737593555..19376bee9ec13 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -48,6 +48,7 @@ #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 #define DWCMSHC_EMMC_DLL_START_POINT 16 #define DWCMSHC_EMMC_DLL_INC 8 +#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA @@ -60,6 +61,7 @@ #define DLL_RXCLK_NO_INVERTER 1 #define DLL_RXCLK_INVERTER 0 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 +#define DLL_RXCLK_ORI_GATE BIT(31) #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) @@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock sdhci_writel(host, extra, reg); if (clock <= 52000000) { - /* Disable DLL and reset both of sample and drive clock */ - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); + /* + * Disable DLL and reset both of sample and drive clock. + * The bypass bit and start bit need to be set if DLL is not locked. + */ + sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); + sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); /* @@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock } extra = 0x1 << 16 | /* tune clock stop en */ - 0x2 << 17 | /* pre-change delay */ + 0x3 << 17 | /* pre-change delay */ 0x3 << 19; /* post-change delay */ sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); -- 2.51.0