From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42F4A1D6AA for ; Wed, 28 Jan 2026 18:26:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624778; cv=none; b=qhMFEWLj8XSwqiAEX394w1FSU94gyhYhC9AK2v3396UDdhVZ+uxYU/PXH02lyXt21ox6Ugx8Aw8cBwPPPWltmNA+l25LhpgEOkz/z1N9TA8uKD2VhvWJ2ma+7y2BAFEdoHk8R8BKUfOMMkw7dm+Vflw8Y7+UIBVIP3JGMfuKBLo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624778; c=relaxed/simple; bh=3Tu68wwl2W4LqyEP5JnDAJPIPQChdnb/NQ8SWmJ1N6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NKFMAQD4Ly0LN8jhfUmtG6PI/Fyvw+CQ4T44tn6AaZYqbZN+5t0anEngtUSH+yVc4AxyozncTt9IxjfDQ/3cf+7hlDTAJKvKpEfbHNld+5lkV5tGPE7ATjjQoKeiBp7UW8xWI+eqZed8aLUC/QWz0MW00QQQSjhy0haEG4fWm4M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kR7OwGZP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kR7OwGZP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53B4AC4CEF7; Wed, 28 Jan 2026 18:26:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769624778; bh=3Tu68wwl2W4LqyEP5JnDAJPIPQChdnb/NQ8SWmJ1N6s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kR7OwGZP08rSkILl72xotwpBSPAR+LziCtY/VriTPIBrOwJCuAnhVXmU/uqJLDMC4 K55EUuq5XGnGu+n52mFEuSPpWUbexiJqRKCnUf51mc01SgVrdHyqAi8OtmacgzClji 0AVRXTmqsY99EZcnCjuendMZbO626KQ3vbCwDXOPfV9bdCNLFlAiOjFM4EvHzoCgfs UxiiHQ+cLCmjg8YMugjR11ll6IJ7EU5cY7m8LwrVe6HMg1dRU9BPSFJMuf8FMDm5ai V52aIAi2S8J17pffihF/MO3N9xq5yShNRQycHLmEgMLOg8fVFCSiRm6HEmUrcypaoT aQJf6bpNVsvjA== From: Sasha Levin To: stable@vger.kernel.org Cc: Shawn Lin , Sebastian Reichel , Yifeng Zhao , Ulf Hansson , Sasha Levin Subject: [PATCH 6.1.y 2/2] mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode Date: Wed, 28 Jan 2026 13:26:15 -0500 Message-ID: <20260128182615.2660161-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260128182615.2660161-1-sashal@kernel.org> References: <2026012749-barrier-oppressor-3ac6@gregkh> <20260128182615.2660161-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Shawn Lin [ Upstream commit 3009738a855cf938bbfc9078bec725031ae623a4 ] When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller requires maintaining a minimum clock of 52MHz in these modes. Add a check to prevent illegal clock reduction through debugfs: root@debian:/# echo 50000000 > /sys/kernel/debug/mmc0/clock root@debian:/# [ 30.090146] mmc0: running CQE recovery mmc0: cqhci: Failed to halt mmc0: cqhci: spurious TCN for tag 0 WARNING: drivers/mmc/host/cqhci-core.c:797 at cqhci_irq+0x254/0x818, CPU#1: kworker/1:0H/24 Modules linked in: CPU: 1 UID: 0 PID: 24 Comm: kworker/1:0H Not tainted 6.19.0-rc1-00001-g09db0998649d-dirty #204 PREEMPT Hardware name: Rockchip RK3588 EVB1 V10 Board (DT) Workqueue: kblockd blk_mq_run_work_fn pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : cqhci_irq+0x254/0x818 lr : cqhci_irq+0x254/0x818 ... Fixes: c6f361cba51c ("mmc: sdhci-of-dwcmshc: add support for rk3588") Cc: Sebastian Reichel Cc: Yifeng Zhao Signed-off-by: Shawn Lin Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-of-dwcmshc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 19376bee9ec13..aa68c63f70243 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -236,6 +236,13 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock sdhci_writel(host, extra, reg); if (clock <= 52000000) { + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || + host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { + dev_err(mmc_dev(host->mmc), + "Can't reduce the clock below 52MHz in HS200/HS400 mode"); + return; + } + /* * Disable DLL and reset both of sample and drive clock. * The bypass bit and start bit need to be set if DLL is not locked. -- 2.51.0