From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DD7421EFE; Wed, 4 Feb 2026 15:13:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770217980; cv=none; b=WjlFO2/u92LPclSSGTcIDw76K0GnxW2Zu0CAPRwjXzD4Pw6VrIngA8exA2caX4/zVGJV5xQh/aRL4pUV8mYLZN7yTyW6oybqK18L1GcPsr1tJWnkz4JAGSiULoPfqAv816uCVo53lrQHxIjRLUuXQ90uENY/NSbsfuve67ZKuF0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770217980; c=relaxed/simple; bh=Fwp8aShMoYTe8WepbfVD07pnX1xXZH3aQ5jZXEPCYe8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f56C5J7vZaTzq/siMyp6a4vf0WL3kjpEMJFinHaqw/LEX8xm8K8D2SIOdVoea5SE71YHzRxy8nX8X9qg1snU+iYPKLLqNBScIaFgAXipGPde9ddrga4+Knhtqg08ikquTA1z5ytyhJjxjlvsna+iiHZWaqttQBRzfqttm/9pdC0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=XfhP9fb9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="XfhP9fb9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA7CBC116C6; Wed, 4 Feb 2026 15:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1770217980; bh=Fwp8aShMoYTe8WepbfVD07pnX1xXZH3aQ5jZXEPCYe8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XfhP9fb9w+V6Ubx2hw24dDtspoNtjJwnWBfmODyvYqP2iFcx29InYdkt5av1akLWj t+jXZw+7yTYq3ocUdvtA9ZT4JO3T6oAeZ1DsMSj4Yly4Oj6zMrjmFaYsAzz/HZNaAV 3KXK/rwwYGNXBXYDVWq6gD5bqStVsQKFAPv7qXD8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, "=?UTF-8?q?Jan=20H . =20Sch=C3=B6nherr?=" , Peter Zijlstra , Fernand Sieber Subject: [PATCH 6.1 177/280] perf/x86/intel: Do not enable BTS for guests Date: Wed, 4 Feb 2026 15:39:11 +0100 Message-ID: <20260204143915.987867790@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260204143909.614719725@linuxfoundation.org> References: <20260204143909.614719725@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Fernand Sieber commit 91dcfae0ff2b9b9ab03c1ec95babaceefbffb9f4 upstream. By default when users program perf to sample branch instructions (PERF_COUNT_HW_BRANCH_INSTRUCTIONS) with a sample period of 1, perf interprets this as a special case and enables BTS (Branch Trace Store) as an optimization to avoid taking an interrupt on every branch. Since BTS doesn't virtualize, this optimization doesn't make sense when the request originates from a guest. Add an additional check that prevents this optimization for virtualized events (exclude_host). Reported-by: Jan H. Schönherr Suggested-by: Peter Zijlstra Signed-off-by: Fernand Sieber Signed-off-by: Peter Zijlstra (Intel) Cc: Link: https://patch.msgid.link/20251211183604.868641-1-sieberf@amazon.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/perf_event.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1421,13 +1421,22 @@ static inline bool intel_pmu_has_bts_per struct hw_perf_event *hwc = &event->hw; unsigned int hw_event, bts_event; - if (event->attr.freq) + /* + * Only use BTS for fixed rate period==1 events. + */ + if (event->attr.freq || period != 1) + return false; + + /* + * BTS doesn't virtualize. + */ + if (event->attr.exclude_host) return false; hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); - return hw_event == bts_event && period == 1; + return hw_event == bts_event; } static inline bool intel_pmu_has_bts(struct perf_event *event)