[PATCH AUTOSEL 6.19] drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35

[Sasha Levin <sashal@kernel.org>]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[ Upstream commit 75372d75a4e23783583998ed99d5009d555850da ]

[Why]
A backport of the change made for DCN401 that addresses an issue where
we turn off the PHY PLL when disabling TMDS output, which causes the
OTG to remain stuck.

The OTG being stuck can lead to a hang in the DCHVM's ability to ACK
invalidations when it thinks the HUBP is still on but it's not receiving
global sync.

The transition to PLL_ON needs to be atomic as there's no guarantee
that the thread isn't pre-empted or is able to complete before the
IOMMU watchdog times out.

[How]
Backport the implementation from dcn401 back to dcn35.

There's a functional difference in when the eDP output is disabled in
dcn401 code so we don't want to utilize it directly.

Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

Here is my complete analysis:

---

## Detailed Analysis

### 1. COMMIT MESSAGE ANALYSIS

The commit subject states: "Adjust PHY FSM transition to TX_EN-to-PLL_ON
for TMDS on DCN35." The body explains this is a backport of a fix
originally made for DCN401 that addresses a critical issue: **when
disabling TMDS output, the PHY PLL is turned off, causing the OTG
(Output Timing Generator) to get stuck**. The stuck OTG leads to a hang
in DCHVM (Display Controller Host Virtual Memory) because the HUBP (Hub
Pre-processor) is perceived as still active but doesn't receive global
sync, causing IOMMU watchdog timeouts.

Key phrases: "OTG being stuck", "hang", "IOMMU watchdog times out" —
this is describing a **system hang** scenario.

The original DCN401 commit `9b68445eb657d` states more explicitly: "If
two monitors with TMDS signals were timing synced and one was
disconnected, the stream would go out of sync too early due to the PLL
turning off and **the system could hang**."

### 2. CODE CHANGE ANALYSIS

The core change is replacing `dcn32_disable_link_output` with a new
`dcn35_disable_link_output` in the DCN35 hardware sequencer function
table.

**Old behavior (`dcn32_disable_link_output`):**
1. Disable the link output via `link_hwss->disable_link_output()` — this
   turns off the PHY **completely** (SYMCLK_OFF_TX_OFF)
2. Set state to `SYMCLK_OFF_TX_OFF`
3. Call `apply_symclk_on_tx_off_wa()` — this is a **workaround** that
   detects if SYMCLK is still needed by OTG, and if so, **re-enables the
   PHY** and programs it to `SYMCLK_ON_TX_OFF`

The old approach has a **race window**: between step 1 (PHY fully off)
and step 3 (PHY re-enabled with PLL on), there's a window where SYMCLK
is off but OTG still needs it. The comment in
`apply_symclk_on_tx_off_wa` itself acknowledges this: *"In future dcn
generations, we plan to rework transmitter control interface so that we
could have an option to set SYMCLK ON TX OFF state in one step without
this workaround."*

**New behavior (`dcn35_disable_link_output`):**
1. **Before** calling `link_hwss->disable_link_output()`, check if this
   is a TMDS signal AND the OTG still references SYMCLK
   (`symclk_ref_cnts.otg > 0`)
2. If yes: **instead of fully disabling**, call
   `disable_link_output_symclk_on_tx_off()` which goes directly to the
   `SYMCLK_ON_TX_OFF` state via `program_pix_clk()` — **atomically**,
   without the intermediate SYMCLK_OFF state
3. If no: proceed with full disable as before

This eliminates the race window entirely. The transition is atomic —
there's never a point where SYMCLK is off while OTG still needs it.

### 3. BUG CLASSIFICATION

This fixes a **system hang / lockup**:
- The OTG gets stuck when SYMCLK disappears while it's still in use
- The stuck OTG prevents DCHVM from ACKing IOMMU invalidations
- The IOMMU watchdog eventually times out, which can cause a **system
  hang**
- This is a race condition — the thread performing the disable can be
  preempted between the PHY-off and re-enable steps

This is a clear bug fix for a **race condition** that causes a **system
hang**.

### 4. SCOPE AND RISK

**Size:** ~72 lines added across 3 files. The new function
`dcn35_disable_link_output` is a self-contained implementation, plus the
helper `disable_link_output_symclk_on_tx_off`, and one line changed in
the function table.

**Risk assessment:**
- The new code is a near-exact copy of `dcn401_disable_link_output`
  which has been in mainline since the DCN401 commit (v6.12 timeframe)
- The only intentional difference from DCN401 is in the eDP handling:
  DCN401 has a second `edp_power_control()` call after the TMDS check,
  while DCN35 keeps the `unlock_phy` pattern from DCN32 — the commit
  message explicitly acknowledges this ("There's a functional difference
  in when the eDP output is disabled in dcn401 code so we don't want to
  utilize it directly")
- The change is purely in DCN35-specific code, so it cannot affect other
  display controller generations
- The function has been **Reviewed-by** (Yihan Zhu) and **Tested-by**
  (Dan Wheeler, AMD's test engineer)

**Risk is LOW**: The pattern is proven on DCN401 and is a surgical fix
to a specific DCN35 function table entry.

### 5. USER IMPACT

DCN35 is AMD's display controller in Ryzen 8000 series (Phoenix/Hawk
Point) APUs — widely deployed in consumer laptops and desktops. Users
with TMDS (HDMI/DVI) displays connected to DCN35-based systems can hit
this hang, especially in multi-monitor configurations where one monitor
is disconnected. This is a **real user-facing hang** scenario.

### 6. DEPENDENCY CHECK

- `dc_is_tmds_signal()`: inline function in `signal_types.h` — available
  in all relevant stable trees
- `get_link_hwss()`: defined in `dc_resource.c` and declared in
  `link_hwss.h` (already included)
- `DP_UNKNOWN_ENCODING`: enum in `dc_dp_types.h` — available
- `SYMCLK_ON_TX_OFF`, `SYMCLK_OFF_TX_OFF`: enums in `dc_hw_types.h` —
  available since DCN32
- `DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY`: available in dpcd_defs

DCN35 code exists in stable kernels starting from **v6.8**. All current
active stable trees that include DCN35 (6.12.y, 6.13.y, 6.14.y)
currently use `dcn32_disable_link_output` and would benefit from this
fix.

The commit is **self-contained** — it adds a new function and wires it
up. No dependency on other patches.

### 7. STABILITY INDICATORS

- **Reviewed-by: Yihan Zhu** — reviewed by AMD display team member
- **Tested-by: Dan Wheeler** — AMD's display test lead
- The original DCN401 implementation has been in mainline since ~v6.12
- The author (Nicholas Kazlauskas) is a well-known AMD display developer

### Summary

This commit fixes a **system hang / lockup** caused by a **race
condition** in the PHY state machine transition for TMDS outputs on
DCN35 (AMD Phoenix/Hawk Point display controllers). The old
`dcn32_disable_link_output` had a race window where SYMCLK could be off
while the OTG still needed it, causing the OTG to get stuck and
eventually triggering an IOMMU watchdog timeout leading to a system
hang. The fix makes the transition atomic by checking the TMDS/OTG
condition upfront and going directly to `SYMCLK_ON_TX_OFF` instead of
the two-step off-then-on workaround.

The fix is small (~72 lines), self-contained, well-tested by AMD, based
on proven DCN401 code, and addresses a real user-facing system hang on
widely deployed hardware. It meets all stable kernel criteria: obviously
correct (modeled after DCN401), fixes a real bug (system hang), small
scope (DCN35-only), and introduces no new features.

**YES**

 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 52 +++++++++++++++++++
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h   |  3 ++
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |  2 +-
 3 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index cb2dfd34b5e2e..88542ca715573 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1726,3 +1726,55 @@ void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe
 {
 	dc_dmub_srv_program_cursor_now(dc, pipe);
 }
+
+static void disable_link_output_symclk_on_tx_off(struct dc_link *link, enum dp_link_encoding link_encoding)
+{
+	struct dc *dc = link->ctx->dc;
+	struct pipe_ctx *pipe_ctx = NULL;
+	uint8_t i;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+		if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
+			pipe_ctx->clock_source->funcs->program_pix_clk(
+					pipe_ctx->clock_source,
+					&pipe_ctx->stream_res.pix_clk_params,
+					link_encoding,
+					&pipe_ctx->pll_settings);
+			break;
+		}
+	}
+}
+
+void dcn35_disable_link_output(struct dc_link *link,
+		const struct link_resource *link_res,
+		enum signal_type signal)
+{
+	struct dc *dc = link->ctx->dc;
+	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
+	struct dmcu *dmcu = dc->res_pool->dmcu;
+
+	if (signal == SIGNAL_TYPE_EDP &&
+			link->dc->hwss.edp_backlight_control &&
+			!link->skip_implict_edp_power_control)
+		link->dc->hwss.edp_backlight_control(link, false);
+	else if (dmcu != NULL && dmcu->funcs->lock_phy)
+		dmcu->funcs->lock_phy(dmcu);
+
+	if (dc_is_tmds_signal(signal) && link->phy_state.symclk_ref_cnts.otg > 0) {
+		disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING);
+		link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
+	} else {
+		link_hwss->disable_link_output(link, link_res, signal);
+		link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+	}
+	/*
+	 * Add the logic to extract BOTH power up and power down sequences
+	 * from enable/disable link output and only call edp panel control
+	 * in enable_link_dp and disable_link_dp once.
+	 */
+	if (dmcu != NULL && dmcu->funcs->unlock_phy)
+		dmcu->funcs->unlock_phy(dmcu);
+
+	dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 1ff41dba556c0..e3459546a908a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -108,5 +108,8 @@ void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe
 void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,
 					    const struct dc_stream_state *stream);
 void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);
+void dcn35_disable_link_output(struct dc_link *link,
+		const struct link_resource *link_res,
+		enum signal_type signal);
 
 #endif /* __DC_HWSS_DCN35_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 5a66c9db26709..81bd36f3381db 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -113,7 +113,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
 	.enable_lvds_link_output = dce110_enable_lvds_link_output,
 	.enable_tmds_link_output = dce110_enable_tmds_link_output,
 	.enable_dp_link_output = dce110_enable_dp_link_output,
-	.disable_link_output = dcn32_disable_link_output,
+	.disable_link_output = dcn35_disable_link_output,
 	.z10_restore = dcn35_z10_restore,
 	.z10_save_init = dcn31_z10_save_init,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
-- 
2.51.0