[PATCH AUTOSEL 6.19-6.1] drm/amd/display: Remove conditional for shaper 3DLUT power-on

[Sasha Levin <sashal@kernel.org>]

From: Alex Hung <alex.hung@amd.com>

[ Upstream commit 1b38a87b8f8020e8ef4563e7752a64182b5a39b9 ]

[Why]
Shaper programming has high chance to fail on first time after
power-on or reboot. This can be verified by running IGT's kms_colorop.

[How]
Always power on the shaper and 3DLUT before programming by
removing the debug flag of low power mode.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

Good. This confirms the key observation: `mpc32_program_3dlut()` at line
927 **already calls `mpc32_power_on_shaper_3dlut()` unconditionally**
for power-on. The fix makes `mpc32_program_shaper()` consistent with
this pattern.

## Analysis

### 1. What the commit fixes

The commit fixes a real hardware programming bug in AMD DCN 3.2 display
hardware (RDNA3 GPUs). The shaper LUT programming
(`mpc32_program_shaper()`) was conditionally gating the power-on of the
shaper/3DLUT memory behind a debug flag
(`enable_mem_low_power.bits.mpc`). When this flag is not set, the
hardware memory is never powered on before programming, causing shaper
programming to fail on first boot or reboot.

### 2. The bug mechanism

Looking at `mpc32_power_on_shaper_3dlut()` (lines 682-709):
- Line 692-693: It **always** writes to `MPCC_MCM_MEM_PWR_CTRL` to
  enable/disable power — this is the actual power control
- Lines 695-698: The debug flag only controls whether to **wait** for
  the power state to settle

The caller `mpc32_program_shaper()` was incorrectly checking the debug
flag before even calling the function, meaning the power control
register was never written when the flag was off. Without powering on
the memory, the subsequent LUT programming writes fail silently.

### 3. Consistency evidence

`mpc32_program_3dlut()` (line 927) already calls
`mpc32_power_on_shaper_3dlut()` unconditionally for power-on. The
conditional only guards the power-**down** (line 987-988). The fix makes
`mpc32_program_shaper()` follow the same correct pattern.

### 4. Stable criteria assessment

- **Fixes a real bug**: Yes — shaper programming fails on first
  boot/reboot, causing incorrect color management
- **Obviously correct**: Yes — makes the shaper function consistent with
  the 3DLUT function's already-correct unconditional power-on
- **Small and contained**: Yes — a single line change (removing one `if`
  condition)
- **No new features**: Correct — just ensures hardware is powered before
  programming
- **Tested**: Yes — `Tested-by: Daniel Wheeler`, verified with IGT
  kms_colorop test, `Reviewed-by: Aurabindo Pillai`
- **Risk**: Very low — the function call always writes the power
  register; removing the guard just ensures it's always called

### 5. User impact

This affects all AMD RDNA3 GPU users (RX 7000 series) who use color
management features (shaper/3DLUT). Failure to program the shaper LUT
means incorrect display color output. This is a functional correctness
issue, not just cosmetic.

### Verification

- Read `mpc32_power_on_shaper_3dlut()` (lines 682-709): Confirmed it
  always writes power register at line 692-693 regardless of debug flag;
  debug flag only controls wait at lines 695-698
- Read `mpc32_program_shaper()` (lines 712-751): Confirmed the buggy
  conditional at line 727 gates the entire power-on call
- Read `mpc32_program_3dlut()` (lines 908-991): Confirmed unconditional
  power-on at line 927, proving the fix makes the pattern consistent
- git log confirmed the file exists in the current tree with DCN32
  support present
- Commit has Reviewed-by and Tested-by tags from AMD engineers

**YES**

 drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
index 83bbbf34bcac7..badcef027b846 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
@@ -724,8 +724,7 @@ bool mpc32_program_shaper(
 		return false;
 	}
 
-	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
-		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
+	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
 
 	current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
 
-- 
2.51.0