[PATCH AUTOSEL 6.19-5.10] drm/radeon: Add HAINAN clock adjustment

[Sasha Levin <sashal@kernel.org>]

From: decce6 <decce6@proton.me>

[ Upstream commit 908d318f23d6b5d625bea093c5fc056238cdb7ff ]

This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from
850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This
patch is for radeon.

Signed-off-by: decce6 <decce6@proton.me>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

Now let me check the existing code to understand the pattern of these
quirks and what the commit adds.

## Analysis

### What the commit does
This commit adds a device-specific clock speed limitation (quirk) for
the AMD Radeon R5 M420 GPU, identified by PCI device ID `0x666f` and
revision `0x00`. It caps the core clock (sclk) to 800 MHz (80000 *
10kHz) and memory clock (mclk) to 950 MHz (95000 * 10kHz), down from the
default 850/1000 MHz, to achieve stable operation.

### Classification: Hardware Quirk
This is a **hardware quirk/workaround** — it follows an existing, well-
established pattern in `si_apply_state_adjust_rules()` where specific
HAINAN and OLAND device IDs/revisions have their clock speeds capped to
prevent instability. The existing code already has multiple similar
entries for other HAINAN variants (0x6664, 0x6665, 0x6667) and OLAND
variants.

### Stable Kernel Criteria Assessment

**Meets criteria:**
- **Fixes a real bug**: Without this quirk, the R5 M420 GPU runs
  unstably at its default clock speeds. This is a stability fix for real
  hardware.
- **Small and contained**: +5 lines, purely additive, in a single file,
  within an existing pattern.
- **Obviously correct**: Follows the exact same pattern as adjacent
  quirk entries.
- **No new features**: This is a workaround for broken hardware, not a
  feature.
- **Low risk**: Only affects the specific device ID 0x666f rev 0x00 —
  cannot impact any other hardware.
- **Accepted by AMD maintainer**: Signed off by Alex Deucher (AMD GPU
  subsystem maintainer).

**Concerns:**
- The commit message says "making it work stably" but doesn't detail
  specific symptoms (crashes, GPU hangs, artifacts, etc.).
- The author (`decce6@proton.me`) appears to be a relatively new
  contributor, and there's no `Tested-by:` or `Reported-by:` tag from
  others.
- However, this exact pattern has been used for years for other HAINAN
  variants, and similar patches have been accepted and even modified
  over time (see commits `c7e5587964201` and `a628392cf03e0`).

### Risk Assessment
**Very low risk**. The change is gated by specific device ID AND
revision checks (`device == 0x666f && revision == 0x00`), so it cannot
affect any other GPU. The pattern is identical to existing, proven quirk
entries. The worst case if the quirk values are wrong is slightly lower
performance on that one specific GPU model — the current state without
the quirk is instability/crashes.

### Verification
- Verified the existing code pattern in `si_apply_state_adjust_rules()`
  at `si_dpm.c:2915-2941` — the new code follows the exact same
  structure.
- Verified commit `c7e5587964201` shows history of HAINAN clock quirk
  adjustments (removing rev 0x83 because it worked stably without
  overrides), confirming this is an established practice.
- Verified commit `a628392cf03e0` dropped an mclk quirk for HAINAN when
  firmware improved, showing these quirks are hardware-specific and
  necessary.
- Verified device 0x666f is not referenced elsewhere in the radeon
  driver (grep found no other matches), confirming no conflicts.
- Could not access full mailing list discussion on lore.kernel.org
  (search only returned index pages).
- The patch was signed off by Alex Deucher, the AMD GPU maintainer,
  confirming maintainer approval.

This is a textbook hardware quirk addition — small, targeted, following
an established pattern, fixing a real stability issue on specific
hardware. These are explicitly called out as appropriate for stable
backporting.

**YES**

 drivers/gpu/drm/radeon/si_dpm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 9deb91970d4df..f12227145ef08 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2925,6 +2925,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
 			max_sclk = 60000;
 			max_mclk = 80000;
 		}
+		if ((rdev->pdev->device == 0x666f) &&
+		    (rdev->pdev->revision == 0x00)) {
+			max_sclk = 80000;
+			max_mclk = 95000;
+		}
 	} else if (rdev->family == CHIP_OLAND) {
 		if ((rdev->pdev->revision == 0xC7) ||
 		    (rdev->pdev->revision == 0x80) ||
-- 
2.51.0