[PATCH 1/8] drm/amd/display: Skip cursor cache reset if hubp powergating is disabled

[PATCH 1/8] drm/amd/display: Skip cursor cache reset if hubp powergating is disabled

[Alex Hung]

From: Benjamin Nwankwo <Benjamin.Nwankwo@amd.com>

[WHY]
On pipe resets, cursor cache resets to sync with power gated hubp.
But dcn42 doesn't power gate hubp which causes a discrepancy
where cursor registers are still enabled while the cache is cleared.
This ultimately leads to a pipe's cursor incorrectly retaining its
enabled state, while the cursor isn't in its viewport

[HOW]
Skip memsets for dpp and hubp cursor caches if either
disable_hubp_power_gate or ignore_pg flags are true

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Benjamin Nwankwo <Benjamin.Nwankwo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c   | 7 ++++---
 drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 6 ++++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
index ce91e5d28956..194dba734cc1 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
@@ -193,9 +193,10 @@ void dpp_reset(struct dpp *dpp_base)
 	dpp->filter_v_c = NULL;
 	dpp->filter_h = NULL;
 	dpp->filter_v = NULL;
-
-	memset(&dpp_base->pos, 0, sizeof(dpp_base->pos));
-	memset(&dpp_base->att, 0, sizeof(dpp_base->att));
+	if (!dpp_base->ctx->dc->debug.ignore_pg) {
+		memset(&dpp_base->pos, 0, sizeof(dpp_base->pos));
+		memset(&dpp_base->att, 0, sizeof(dpp_base->att));
+	}
 
 	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
 	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index 6378e3fd7249..a2ddf81538e6 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -548,8 +548,10 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
 
 void hubp_reset(struct hubp *hubp)
 {
-	memset(&hubp->pos, 0, sizeof(hubp->pos));
-	memset(&hubp->att, 0, sizeof(hubp->att));
+	if (!hubp->ctx->dc->debug.ignore_pg && !hubp->ctx->dc->debug.disable_hubp_power_gate) {
+		memset(&hubp->pos, 0, sizeof(hubp->pos));
+		memset(&hubp->att, 0, sizeof(hubp->att));
+	}
 	hubp->cursor_offload = false;
 }
 
-- 
2.43.0

[PATCH 2/8] drm/amd/display: Fallback to boot snapshot for dispclk

[Alex Hung]

From: Dillon Varone <Dillon.Varone@amd.com>

[WHY & HOW]
If the dentist is unavailable, fallback to reading CLKIP via the boot
snapshot to get the current dispclk.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 95d9e17a269b..69cc70106bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -72,7 +72,11 @@ void dcn401_initialize_min_clocks(struct dc *dc)
 		 * audio corruption. Read current DISPCLK from DENTIST and request the same
 		 * freq to ensure that the timing is valid and unchanged.
 		 */
-		clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+		if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {
+			clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+		} else {
+			clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;
+		}
 	}
 	clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
 	clocks->fclk_p_state_change_support = true;
-- 
2.43.0