From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DA904C042E; Sat, 28 Feb 2026 17:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300093; cv=none; b=E9hEiDsalss57+He3i7+xy1+MHKK+tQGnZsnWHEPDE/gV702FPOen7+PLncpP2bJ6hFo1gpriJqu7DC53nAGojWlOJwhCCh03puv9Pt0fyTRCQMk08y2alsCxNPL+IJxdAA7TXifQkdzk6SsiZEnhrlRPu89GT0Zyl8AEhQaHEs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300093; c=relaxed/simple; bh=Ix2tqAtDfLsARaykkaLnpch4kUaJMJ6GE7Rk6SrSrnc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qYGMAtYyzEji5PXpoCdU4WDl3F7RNovIXCaueQEmKR/GvfFkwd8G3JKCXD90023SpynJokv7mR5FqeHMNSIr7+HnQME2FemW77389pW3qcRwkHlnDn40uNyN+SbcKRlXeqQzwxqUOoi8ZrrGAWP11bHzPlN2Ws29qonB6VD3Yjw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hGAY53nJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hGAY53nJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6933BC19423; Sat, 28 Feb 2026 17:34:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300093; bh=Ix2tqAtDfLsARaykkaLnpch4kUaJMJ6GE7Rk6SrSrnc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hGAY53nJKJZ+plk62JEKoWdbtIjfpDcGkAwSl6+0uWj7UyncoRveT2iTZqUCn6zvc 8lBl+jvhgZ/TiO7Cr23dbURI+txD5WOrbEXEluDd6rhtUUbyeAEMgDlPkBqXU+xHcx IlzANQ26IGYgRBXBmUquaj6cFYAZbgzGgHa7pB8sh6StHl01efLgyJL8CwYjm9HRs+ ns+apv45jhYgYOSLbQHMG4IymqKBoxJ+3uwaqF+t2xJpNO3KNLDD3iPse/ZezikHXS mIYPcDkNs/N4JHkzZCPUXSpi+5pT0TtyFO1BCLFwaOCLSChddfU3mxHCInh41viBL/ EINJ0Q/X0WC9A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Chenghai Huang , Herbert Xu , Sasha Levin Subject: [PATCH 6.19 108/844] crypto: hisilicon/qm - move the barrier before writing to the mailbox register Date: Sat, 28 Feb 2026 12:20:21 -0500 Message-ID: <20260228173244.1509663-109-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Chenghai Huang [ Upstream commit ebf35d8f9368816c930f5d70783a72716fab5e19 ] Before sending the data via the mailbox to the hardware, to ensure that the data accessed by the hardware is the most up-to-date, a write barrier should be added before writing to the mailbox register. The current memory barrier is placed after writing to the register, the barrier order should be modified to be before writing to the register. Signed-off-by: Chenghai Huang Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/crypto/hisilicon/qm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index b8e59f99f7007..cf58d0d01b199 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -609,9 +609,13 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) } #if IS_ENABLED(CONFIG_ARM64) + /* + * The dmb oshst instruction ensures that the data in the + * mailbox is written before it is sent to the hardware. + */ asm volatile("ldp %0, %1, %3\n" - "stp %0, %1, %2\n" "dmb oshst\n" + "stp %0, %1, %2\n" : "=&r" (tmp0), "=&r" (tmp1), "+Q" (*((char __iomem *)fun_base)) -- 2.51.0