From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB8DB37147D; Sat, 28 Feb 2026 17:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300143; cv=none; b=sUh3ywEqO4vXJdMvl5h+j3HNihWgQP2BEDcEibInCenQPIwVblF0meu7F6jekKBqYMJDqAbntjKE27FNrwL0SnzvxaE842BnUboYkwhTQWlXudsMPs59Fhp8qwJcjr25Re6fct2imHDl6yrHTpSVbb7V6VHiDb+lXbnolMut704= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300143; c=relaxed/simple; bh=JWeOc0Lbdei6aIrRvm6tRFwtITZbAgHUhPg0VYB4LpI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eT/BzlUC3sdrH3mZ7IdyLnsHeqqtuigOKa+wLLffleLJ+k+JYNoHaadyB8Wo/aL7whKYFXGZAjahs824ZwuCMTRFBtOk3lv+SMkG/NLY8OOZExtr4veuLJ6MnGzzVL1sXbbx175p6F586M0b2W/7jpFCOec8hKpT9BgQMifvf/I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SClNR+qN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SClNR+qN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92626C19423; Sat, 28 Feb 2026 17:35:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300143; bh=JWeOc0Lbdei6aIrRvm6tRFwtITZbAgHUhPg0VYB4LpI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SClNR+qNXfwZp/K1OB6/BxLiTupUizPsG7B2macYcAI1Uk1ijZtN53d2LCZ9tlo39 6i0Ahf7N8Hi55R6HuItmsY5ITiirSF0FvD0d9BqZmZvRWWdM/YRU04ofoNOFE3YeuD C24ki0083rL5uJPaysTjSy8ywVnD/zJmGl1bA6s/s37rceNGnnzHZMcC3H92pEyUbI EIdLB5eN3TU1hDwdjxaO9ekOpA/uPLCypNy5tj91CRnMsfPRLeEOAMNbISf3rICvyw DgCPuiLx6fFCVW3OeFwQq3yQD88WBshe2Vm1Cw/EXsHg+yArQTNJaLpQK4vjo/QoyZ 18qdHH+YSpQeA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Charlene Liu , Mohit Bawa , Chenyu Chen , Daniel Wheeler , Alex Deucher , Sasha Levin Subject: [PATCH 6.19 161/844] drm/amd/display: Fix dsc eDP issue Date: Sat, 28 Feb 2026 12:21:14 -0500 Message-ID: <20260228173244.1509663-162-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Charlene Liu [ Upstream commit 878a4b73c11111ff5f820730f59a7f8c6fd59374 ] [why] Need to add function hook check before use Reviewed-by: Mohit Bawa Signed-off-by: Charlene Liu Signed-off-by: Chenyu Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 5896ce5511ab1..9f7087ac41f21 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1797,6 +1797,9 @@ static void disable_vga_and_power_gate_all_controllers( struct timing_generator *tg; struct dc_context *ctx = dc->ctx; + if (dc->caps.ips_support) + return; + for (i = 0; i < dc->res_pool->timing_generator_count; i++) { tg = dc->res_pool->timing_generators[i]; @@ -1873,13 +1876,16 @@ static void clean_up_dsc_blocks(struct dc *dc) /* disable DSC in OPTC */ if (i < dc->res_pool->timing_generator_count) { tg = dc->res_pool->timing_generators[i]; - tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); + if (tg->funcs->set_dsc_config) + tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); } /* disable DSC in stream encoder */ if (i < dc->res_pool->stream_enc_count) { se = dc->res_pool->stream_enc[i]; - se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); - se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); + if (se->funcs->dp_set_dsc_config) + se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); + if (se->funcs->dp_set_dsc_pps_info_packet) + se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); } /* disable DSC block */ if (dccg->funcs->set_ref_dscclk) -- 2.51.0