From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD4F046AEF1; Sat, 28 Feb 2026 17:33:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300007; cv=none; b=OoyUTvYevpBUJ4KWCmwkw5X/4gj4DJm6v43WvEjubuZottYfObfXljG4WFhzqT8KS2d/FYxPtbxMHClkZaZDiTIi6ov5KNxn3xylxnifcasvCdMJL5HM8MPdGbyZ8fhkhGonJ1/BhbmXbSkLBJ9aSjxlHO66CrOcHxjDH6goU7g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300007; c=relaxed/simple; bh=5DLthrwaQ4P8bCT3/l3haLmoSWFTHHexrJJVVVyJFYI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y96rw9RKfa4TiH6vG+kplc0nUV3Di7CMJWJF1NMpOtqWLFrm5xKNnZURfEfeJ4gkID7VaBAw2ehjLvo9ObtH7ZsxYttcLfpS1tcsuwK5uSAcLsepUI3kVhFbZt0BPWHHr1criqAvoPFY/BUET/2IaK+uaUl1a+VEYS0LMGYm/mY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s4Y56Ajc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s4Y56Ajc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9476C19423; Sat, 28 Feb 2026 17:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300007; bh=5DLthrwaQ4P8bCT3/l3haLmoSWFTHHexrJJVVVyJFYI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s4Y56AjckbpHTsvZ651IA1MDdRUUhMZ8mw+YX23J7cQreEXxPfO4yLIfV2dacLqjj +65QfSUQTWauvXomaCqcqT1Qa1pdFjbsw4uTSSv7WYr8+KehbWQohZwecfbL/ZTFEG INBJepPP8M7POQvxph+3kJqUhZUNV50ePDs9/XXvOumNSvigONXBtmRUd5aXSope9A tBiKKUHoZnle3g3une4UuX4VymxmQB0GrXhbzzZu11s3EHmwwGx+IFON73YVTkohXH ym8bO9mxcxEOJkMvjEsX3FlzwY9tUR78sKeYFwFktvrKThG1j6GXskUJV9iyLgUeu3 mTQ4c3NWmQ/7Q== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sandipan Das , Suyash Mahar , Ian Rogers , Adrian Hunter , Alexander Shishkin , Ananth Narayan , Ingo Molnar , James Clark , Jiri Olsa , Mark Rutland , Namhyung Kim , Peter Zijlstra , Ravi Bangoria , Arnaldo Carvalho de Melo , Sasha Levin Subject: [PATCH 6.19 023/844] perf vendor events amd: Fix Zen 5 MAB allocation events Date: Sat, 28 Feb 2026 12:18:56 -0500 Message-ID: <20260228173244.1509663-24-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Sandipan Das [ Upstream commit 76b2cf07a6d2a836108f9c2486d76599f7adf6e8 ] The unit masks for PMCx041 vary across different generations of Zen processors. Fix the Zen 5 events based on PMCx041 as they incorrectly use the same unit masks as that of Zen 4. Fixes: 45c072f2537ab07b ("perf vendor events amd: Add Zen 5 core events") Reported-by: Suyash Mahar Reviewed-by: Ian Rogers Signed-off-by: Sandipan Das Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ananth Narayan Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/pmu-events/arch/x86/amdzen5/load-store.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/amdzen5/load-store.json b/tools/perf/pmu-events/arch/x86/amdzen5/load-store.json index ff6627a778057..06bbaea159259 100644 --- a/tools/perf/pmu-events/arch/x86/amdzen5/load-store.json +++ b/tools/perf/pmu-events/arch/x86/amdzen5/load-store.json @@ -70,19 +70,19 @@ "EventName": "ls_mab_alloc.load_store_allocations", "EventCode": "0x41", "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.", - "UMask": "0x3f" + "UMask": "0x07" }, { "EventName": "ls_mab_alloc.hardware_prefetcher_allocations", "EventCode": "0x41", "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.", - "UMask": "0x40" + "UMask": "0x08" }, { "EventName": "ls_mab_alloc.all_allocations", "EventCode": "0x41", "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.", - "UMask": "0x7f" + "UMask": "0x0f" }, { "EventName": "ls_dmnd_fills_from_sys.local_l2", -- 2.51.0