From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29EBD3B3418; Sat, 28 Feb 2026 17:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300318; cv=none; b=AydGjPAcHiLjVsz1M0N/aQfSjumwGbrZYVHRQwPc6saLoKPKv8lUG9pBMeGZGU5nOjXat4CLu4cJcXJEbs36dxxcAf6kbsgd6fIizK9FPOnhpY9ctcQerZ/euQImNr2oDSOSEamfXHNgL/BkIjfYICIquKKoPvQq0wRQAY9T5Aw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300318; c=relaxed/simple; bh=RcdWu7BakA3IUxlBsPgkVxCtelqX2FgPXyoYVc88DP8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AtBL+D1iwk6d4hhP3lrIRttZzfLwSs99OJgNvKLh2+qdj9aQhFO/B+XlDGZKH9NgljwNzR+WwWA4lQqK+h8+Bq0ILftrayGkTjyatuR8c7ozP4Wzvf28Yg8FBf7TW46aCYiJtM+c4SjkLKDAmR3+UsrJ7/plLV+PkOMDZI9eozk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QsUkqrKu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QsUkqrKu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62D9BC4AF09; Sat, 28 Feb 2026 17:38:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300318; bh=RcdWu7BakA3IUxlBsPgkVxCtelqX2FgPXyoYVc88DP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QsUkqrKuBifVIxxCh6TK062IgahDaC7/vuRe/GOtuIWHCt+g3ildgicaInzKLrqid 0DcOMnohpj1YDlDp81KRTR+A9o5K3JZhdG1bdaLcms0E1UTA/67OF+Q2QsU72tuvO1 yL/3eTD5MFjW6RXvtZksu6pMdw2fqfQc45XBz8uYHwcPNyZ3eWdzjOGLqWuzjyvj7V cJyTxtI/RqE/jjhMYt8KPxhbWyjfBLHpQHSfEUScMb8AuLqHwTwwzUBJa/eQBZqFXQ kLlfrl86YwzMjwf3LAMdpDlLVcW3lJmSghVIqtu/VxeRxkTDoI471Rm3HWi+QGp9jE jK+L171zOEEWA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sergey Matyukevich , Andy Chiu , Paul Walmsley , Sasha Levin Subject: [PATCH 6.19 349/844] riscv: vector: init vector context with proper vlenb Date: Sat, 28 Feb 2026 12:24:22 -0500 Message-ID: <20260228173244.1509663-350-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Sergey Matyukevich [ Upstream commit ef3ff40346db8476a9ef7269fc9d1837e7243c40 ] The vstate in thread_struct is zeroed when the vector context is initialized. That includes read-only register vlenb, which holds the vector register length in bytes. Zeroed state persists until mstatus.VS becomes 'dirty' and a context switch saves the actual hardware values. This can expose the zero vlenb value to the user-space in early debug scenarios, e.g. when ptrace attaches to a traced process early, before any vector instruction except the first one was executed. Fix this by specifying proper vlenb on vector context init. Signed-off-by: Sergey Matyukevich Reviewed-by: Andy Chiu Tested-by: Andy Chiu Link: https://patch.msgid.link/20251214163537.1054292-3-geomatsi@gmail.com Signed-off-by: Paul Walmsley Signed-off-by: Sasha Levin --- arch/riscv/kernel/vector.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 3ed071dab9d83..b112166d51e9f 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -111,8 +111,8 @@ bool insn_is_vector(u32 insn_buf) return false; } -static int riscv_v_thread_zalloc(struct kmem_cache *cache, - struct __riscv_v_ext_state *ctx) +static int riscv_v_thread_ctx_alloc(struct kmem_cache *cache, + struct __riscv_v_ext_state *ctx) { void *datap; @@ -122,13 +122,15 @@ static int riscv_v_thread_zalloc(struct kmem_cache *cache, ctx->datap = datap; memset(ctx, 0, offsetof(struct __riscv_v_ext_state, datap)); + ctx->vlenb = riscv_v_vsize / 32; + return 0; } void riscv_v_thread_alloc(struct task_struct *tsk) { #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE - riscv_v_thread_zalloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate); + riscv_v_thread_ctx_alloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate); #endif } @@ -214,12 +216,14 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) * context where VS has been off. So, try to allocate the user's V * context and resume execution. */ - if (riscv_v_thread_zalloc(riscv_v_user_cachep, ¤t->thread.vstate)) { + if (riscv_v_thread_ctx_alloc(riscv_v_user_cachep, ¤t->thread.vstate)) { force_sig(SIGBUS); return true; } + riscv_v_vstate_on(regs); riscv_v_vstate_set_restore(current, regs); + return true; } -- 2.51.0