From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B064E3E8886; Sat, 28 Feb 2026 17:41:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300513; cv=none; b=BrXPTdeS+TM4U4tnik9XNZKxNFRwvUfGXk3/NlDBhu5mO7CGuQe+25r8lnnGIa2guGkcRF76sNXy7+4jcbTHDwPoIgkCSgA349bbWObY6jgx79Nj1wg9w6joUsASh11KkqgE70RRJdcjp9NaBX3DeCLfs3nF9+Dc4Hj1W3iF4Mk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300513; c=relaxed/simple; bh=TtWiXUJEcIzPQTPR8skO0mNuCG8o8MRv7xf2wd9NKls=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uCnSNJxYJvJX6ghUe86v2aRW9JdzMZ6upgYcpIE6ghuxCJLDMX6PP6KfR4EQ/TXcFCxReooKqDxFunT+ZlelKMRSzrVBFYnOq4F0gt+lkcDMj0oqU86iIB0Nb2cpeDKvGvz7VXmSl6yLFiFKvo4LzMRuZSZdGj+HY7SAcddY3IE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mzLMXSvx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mzLMXSvx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C98BCC2BC87; Sat, 28 Feb 2026 17:41:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300513; bh=TtWiXUJEcIzPQTPR8skO0mNuCG8o8MRv7xf2wd9NKls=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mzLMXSvxeAlrZZXQENWFQpgocOvx0eEHfCUsMjL8t2sc01FS4f12t3vl+FK2PSVT5 VrelEiYGaXuvGSRRsVB9Qfj2PUneJU8LFn1P8ggcNv7kGdx+WinazszPSwGxot00gZ ZCUIpgpPLczog9T4X8SOJZmkPjt4gM5EBI0I4Mx7dXzdNcGtJIFT6fnjIEqiBcb3Tw qvvSouJD3Vfa4mVPS7FEG8FUgux4AjEHgmwkoNkDqLiWPTgsLeW6PWdQupdhFd8GzT l0UZNnYWJngQeAwt35Y62KJ85R8phr/511CCv9/LxUzE8qItdkJhVbtJWApl+Kly6y qruGUe34XD9cQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Abel Vesa , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.19 551/844] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs Date: Sat, 28 Feb 2026 12:27:44 -0500 Message-ID: <20260228173244.1509663-552-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Abel Vesa [ Upstream commit 0907cab01ff9746ecf08592edd9bd85d2636be58 ] The DP PHYs on X1E80100 need the ref clock which is provided by the TCSR CC. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So lets attach it to each of the DP PHYs in order to do that. Cc: stable@vger.kernel.org # v6.9 Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20251224-phy-qcom-edp-add-missing-refclk-v5-3-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 83a0a0c3239d2..9e0934b302c3e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5896,9 +5896,11 @@ mdss_dp2_phy: phy@aec2a00 { <0 0x0aec2000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; @@ -5916,9 +5918,11 @@ mdss_dp3_phy: phy@aec5a00 { <0 0x0aec5000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; -- 2.51.0