From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43E363EEEDD; Sat, 28 Feb 2026 17:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300529; cv=none; b=QPTR3ZIdZrQe1MLNLYJVTLVo9wG2wIHQ731BGp47i2ccRGJhNhmdAMGLHmSKRG+1Yvq/hYwtCl/DDhRVt2VimzeBkOgoCPGhMJeJOc8cqZ7qjhyH4auDUExnhxzy5TJBwXx0jn8sGZwdKy79EU8clscaufRxcAHKWU51bLFKTh0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300529; c=relaxed/simple; bh=IS53KTBMWo9ydqeW1BFesdWD63Lb5PcC6ZpjJOHuW68=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NukdcDSJTnWYX3jCxXmg35TMm6HkWkV08rsOgV7qy3y5mCx84/LAMBz5G0E9tyYDPue5buVlSLVlGSbKLNmS/nNCbdimK5HnyGtjq1eXecSXSm+ZxV9aU1id217XwDpZTc+gJRYTdYdnMqJQY7KskLnN9DW9vcnTqaJnacKtAE8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RUl2hEgb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RUl2hEgb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65B5AC19424; Sat, 28 Feb 2026 17:42:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300529; bh=IS53KTBMWo9ydqeW1BFesdWD63Lb5PcC6ZpjJOHuW68=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RUl2hEgbI0ToHdwfx59xVuZZ7w57Pm3MDFQmWK6QeulnhQ0DYaZzt5fZtsNupWQDk /5Mrq9rY91BXR2rSkAr0wvtD/VEpyvbfCcJHOK78JQJa6no0ywa2Pcg5pVx9ZmcuIB V9DTIg0Rbo7tp3ICJpBWRJP9qtmIqaCKVLj6WzzBieg8A+FUOuI77vIiU6FSQouar5 n5QvcBbtGzcAj1P3N8AOKTfxd8+roU6nflsxVDoeY8F69Q0+rGAtBvYubV9UDpMxOX JVzEJiI4koC8yAnlUC8uGKqUXic40h0AQjKBxzhsVZihK4jubHQk2P6+TB1QNFtvEe ir+VelTqBuF2A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Benjamin Gaignard , Jianfeng Liu , Nicolas Dufresne , Hans Verkuil , Sasha Levin Subject: [PATCH 6.19 568/844] media: verisilicon: AV1: Set IDR flag for intra_only frame type Date: Sat, 28 Feb 2026 12:28:01 -0500 Message-ID: <20260228173244.1509663-569-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Benjamin Gaignard [ Upstream commit 1c1b79f40ee4444fa1ac96079751608b724c6b2b ] Intra_only frame could be considered as a key frame so Instantaneous Decoding Refresh (IDR) flag must be set of the both case and not only for key frames. Signed-off-by: Benjamin Gaignard Reported-by: Jianfeng Liu Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder") Cc: stable@vger.kernel.org Reviewed-by: Nicolas Dufresne Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c index f52b8208e6b93..500e94bcb0293 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -2018,7 +2018,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) !!(ctrls->frame->quantization.flags & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT)); - hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type); + hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type)); hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx); hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8); hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8); -- 2.51.0