From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07220404701; Sat, 28 Feb 2026 17:43:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300635; cv=none; b=gQHXCNUe5BLhjelsKFMzgMQL5cU0UFg7NX1VrVT4juyQgC2+pt8fIys73Povmp0nfNSMOT/rXxNrx3v5/vnKriyMHdT58kZgvNEUiHpgYd0rTXkFXoCnawQrIbVmtZ85lG+KwXlSrvlcjk2DNLL1wjZutEnieUnVBeM11CvTYZw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300635; c=relaxed/simple; bh=i0hec5elO3Uy2H1s2O7ojzDBcoo/YFdHOGcSU5X+kjo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YB6bgHmgagASVuSHT0rAr/ZiUFJ2pUbKo1ukdPaVgT4jUMd5cScIar21PxiGjjGOCFkRLzg1ikaEk1Ty48IHN+LmW2peZGCw3gkrj5YZwismEMABPOUt/vnCceOyiv5rEaBTulNQ/5Qkl8E2ik3LkmLnnn2Pd41z7kSKrxw0UWI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=toFpVqd7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="toFpVqd7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9921C2BC87; Sat, 28 Feb 2026 17:43:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300634; bh=i0hec5elO3Uy2H1s2O7ojzDBcoo/YFdHOGcSU5X+kjo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=toFpVqd7B+T3Li5JVAQRsk4gYhWIUrWw+/giuxEscmBhQ9Pf0otrVhV8HORLyBczR /I3QS4lRAKtVJOEWxV9cP2Gm3fB3x6suQuBkOoOcsS6iYsjwLc8Shd30U90OPuNom5 aUPH4NFQm9QrQTlrwsOYLKJ2E/YpeJ5HVEmCBrjI7Htt7TcPpVuU1esBRJze+WIIGX 7BCKADoqrxCdx+GT9vuVwnL2GIMHN3X3/i4JNAV3UngERMbbUyf/MvDIFg32gdZWFD AdgDQVHDT/HLq5pcsXLTT4PvE+dtVP0M+Jd0Fgvc10vPL0ZlNWpA0kaLMHuFwijzQ5 S0hCipnuQmuaQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jason Gunthorpe , Shuai Xue , Mostafa Saleh , Pranjal Shrivastava , Nicolin Chen , Will Deacon , Sasha Levin Subject: [PATCH 6.19 675/844] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence Date: Sat, 28 Feb 2026 12:29:48 -0500 Message-ID: <20260228173244.1509663-676-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Jason Gunthorpe [ Upstream commit f3c1d372dbb8e5a86923f20db66deabef42bfc9d ] Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV == 0. So mark STE MEV safe when computing the update sequence, to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Reviewed-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 56420104e154e..65c0119f45eae 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1097,6 +1097,16 @@ VISIBLE_IF_KUNIT void arm_smmu_get_ste_update_safe(const __le64 *cur, const __le64 *target, __le64 *safe_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can relax it + * when computing the ordering. The spec notes the device can act like + * MEV=1 anyhow: + * + * Note: Software must expect, and be able to deal with, coalesced + * fault records even when MEV == 0. + */ + safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV); } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); -- 2.51.0