From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA2141651E; Sat, 28 Feb 2026 17:45:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300716; cv=none; b=GcRQI82azpF8nbdU2RHSEkIRnLi/blkgWUgAqTa4wP0e7KCyS4S58TrgZ0ciwIZQw4eH1KbzrH5QeiwIgQsdoSYZ2PNjXes0A6kXRmsMDWSZs9gzvjLwhYxhTJsEXwcFjnuAvUwIfzL+Aoum2YiGs5nRo6Ox66frH2wbL9zvGhs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772300716; c=relaxed/simple; bh=AhMIT7OoY6+ia1wzwEj6LDd5nymD3tVV7EHUtUD+8VE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NSgUowh36pZMIjgPF5YrBsbmkbmcZvdux8EEffS8GMbY9fm6PzbmyYc0o5n3ZLt+547SAo4tQz7ihLI1qpIYeaLPhfF/g6WqKGxl+JGG6+VZ9k/17goAMSoSeZWgUFYDTikVtGBtb3IFBfrVVloCLqEGmrgCuF4lfrYCCYhOXnE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qSQrtyXY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qSQrtyXY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06284C19423; Sat, 28 Feb 2026 17:45:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772300716; bh=AhMIT7OoY6+ia1wzwEj6LDd5nymD3tVV7EHUtUD+8VE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qSQrtyXY/GjQvkY/VZ9nr3IkgirltLG98TEnNwdMbOBMjNYVRWSkw+dv3HYA92J6b KaQTAQ6UwQqEJASY4PmEjXTWjTcdtL6MFLXN3FIBTFKhg3THqxeKSjHxJGx4Hw/XyB 4bUHYTPbisPjhzL6i5fLZczNV4Hnxbu+nMVXpDjNLBp6XL4lk3ic4PSh/D9zwzJDhP KXY/C05uZrl7m1VexzetaIOSASm2MHOC4rUAKaWrg6bNhUaG/0zQa1hw3rWVjLPUr8 lBQ4XdILZWrMwAOHdYIrC4ynjW7cev7aUFK2/THtWBMNgult3Eq7ANhTi3BVf4dXe6 L2SRiB9BaXKPA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Philip Yang , =?UTF-8?q?Christian=20K=C3=B6nig?= , Alex Deucher , Sasha Levin Subject: [PATCH 6.19 752/844] drm/amdgpu: Use 5-level paging if gmc support 57-bit VA Date: Sat, 28 Feb 2026 12:31:05 -0500 Message-ID: <20260228173244.1509663-753-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228173244.1509663-1-sashal@kernel.org> References: <20260228173244.1509663-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Philip Yang [ Upstream commit 3b948dd0366a0b64c02e4ed1aefdf7825942e803 ] Regardless if CPU enable 5-level paging, GPU vm use 5-level paging if gmc init with 57-bit address space support, because ARM64 4-level paging support 48-bit VA, x86 and GPU 4-level paging support 47-bit VA, require 5-level paging on GPU to support ARM64. NPA address space 52-bit mapping on NPA GPU VM require 5-level paging. Debugger trap get device snapshot expect LDS and Scratch base, limit above 57-bit, which is set only for 5-level paging. Signed-off-by: Philip Yang Reviewed-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.19.x Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4d329454456bc..bd7f83efed187 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2360,26 +2360,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, unsigned max_bits) { unsigned int max_size = 1 << (max_bits - 30); - bool sys_5level_pgtable = false; unsigned int vm_size; uint64_t tmp; -#ifdef CONFIG_X86_64 - /* - * Refer to function configure_5level_paging() for details. - */ - sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57); -#endif - - /* - * If GPU supports 5-level page table, but system uses 4-level page table, - * then use 4-level page table on GPU - */ - if (max_level == 4 && !sys_5level_pgtable) { - min_vm_size = 256 * 1024; - max_level = 3; - } - /* adjust vm size first */ if (amdgpu_vm_size != -1) { vm_size = amdgpu_vm_size; -- 2.51.0