From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB44D44CF37; Sat, 28 Feb 2026 17:54:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772301294; cv=none; b=qGXImsdCvljO9d20EPnuvzHXnkjJ0ghqJksA9VWwD8tQd/Ef9tkyj1UyungsuQtFOk4GfXTMTgnXSc0ok5JM2bmIGGs40/zx0QQledtgABrHKh7o+Ld9c+/Dlh+fZek4OZPHvRSWkGZLx1zKTQ4Gn9yFotHRCuyTJJjqqhFKdno= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772301294; c=relaxed/simple; bh=FbUwHqWJZ1clU++cKGaAtloRHsD74SCvaxpYluc92Qg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QD7dxSGJisjZrqzEPUmZbNUQfvAwaxbi3LWHUYbCil33bhFkTflU1K38aHOBlmyfGqPSTLnLBSnmCyx8cXJQirInUfElnS3h0WAiWymV8Yfee10VzZA6y8mn/NT29ZotQ/gq2j+Gy2+YjXAZsk7yIQ9mViItlHLjjj+1Z8nzzF4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sW0sLuB5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sW0sLuB5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1346AC19424; Sat, 28 Feb 2026 17:54:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772301293; bh=FbUwHqWJZ1clU++cKGaAtloRHsD74SCvaxpYluc92Qg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sW0sLuB5SNLaj23k3it8wJNR9GZAKHp2NnLdm6a8EQQvRM6x+xyaxE0GXcFA7qKE9 jsvC0Q0QfqYKPzUPDBAb9Z1VAel1TNYpDcHuN+elGDBREZ0/9w3aNFSrv4Hk2aJa+K x8mPeSnvwP8XCIYQqlylp96DzjkCYppS7qjhC7G8q3rtstNPR7sojul7u8siyjNhA/ DPECIataTOR1GXK4h6PXMro0TGB0tdrR0k3uuLM1hI5+SPjgA3/MudoI2vdzKMQ8EB tJjsb21wNkOhJaDu6S1hUqh7PAeEfjgCTElhJdiEria78iP02I4C0prLyhbKuNDfxR A6Xqz2HJks2rg== From: Sasha Levin To: patches@lists.linux.dev Cc: Abel Vesa , stable@vger.kernel.org, Dmitry Baryshkov , Bjorn Andersson , Vinod Koul , Sasha Levin Subject: [PATCH 6.18 478/752] phy: qcom: edp: Make the number of clocks flexible Date: Sat, 28 Feb 2026 12:43:09 -0500 Message-ID: <20260228174750.1542406-478-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228174750.1542406-1-sashal@kernel.org> References: <20260228174750.1542406-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Abel Vesa [ Upstream commit 7d51b709262c5aa31d2b9cd31444112c1b2dae03 ] On X Elite, the DP PHY needs another clock called ref, while all other platforms do not. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So in order to handle these clocks on different platforms, make the driver get all the clocks regardless of how many there are provided. Cc: stable@vger.kernel.org # v6.10 Fixes: db83c107dc29 ("phy: qcom: edp: Add v6 specific ops and X1E80100 platform support") Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-missing-refclk-v5-2-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/qualcomm/phy-qcom-edp.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index f1b51018683d5..06a08c9ea0f70 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -103,7 +103,9 @@ struct qcom_edp { struct phy_configure_opts_dp dp_opts; - struct clk_bulk_data clks[2]; + struct clk_bulk_data *clks; + int num_clks; + struct regulator_bulk_data supplies[2]; bool is_edp; @@ -218,7 +220,7 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) return ret; - ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); + ret = clk_bulk_prepare_enable(edp->num_clks, edp->clks); if (ret) goto out_disable_supplies; @@ -885,7 +887,7 @@ static int qcom_edp_phy_exit(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); - clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); + clk_bulk_disable_unprepare(edp->num_clks, edp->clks); regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); return 0; @@ -1092,11 +1094,9 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) if (IS_ERR(edp->pll)) return PTR_ERR(edp->pll); - edp->clks[0].id = "aux"; - edp->clks[1].id = "cfg_ahb"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); - if (ret) - return ret; + edp->num_clks = devm_clk_bulk_get_all(dev, &edp->clks); + if (edp->num_clks < 0) + return dev_err_probe(dev, edp->num_clks, "failed to get clocks\n"); edp->supplies[0].supply = "vdda-phy"; edp->supplies[1].supply = "vdda-pll"; -- 2.51.0