From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09A8B1E2606 for ; Sun, 1 Mar 2026 01:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772327864; cv=none; b=YMl4aOHL5hB0rR60Ab7ALXlzx4BsnOy8kKq2I1gaDBj7QQGisjo3Khex9qGwGVrwko6P101NGogespv8rQTP3WVj8ErMkh64KRuLgiN3TPrB/J8HTV8W0NEckHerxrMjWj6O68hgmFQFYZUEgr+lpiyjyWEhTVusEW/aqIwJzlo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772327864; c=relaxed/simple; bh=Gpp3g3wntO4Qc0y0xYsd/8EEdtn7INOVjn/nknEVZ/k=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=RGoEpwXa3AcQ81PPFS4d9j97gBkh/juLpfZs6O1hIDlAFjECQt7a9b3XM1uq8R8PL6ajPHsvxj/G9e+fjhhtZlZ/l6EgbGzETyqbOUtcXbHi+orYznND07NMfjxzEK7+hPAfEzVAdkH95gD0ZcEpAiKmwbGXRJ8K0Dg3TwHd5Sg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h0Z2SKvh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h0Z2SKvh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 002C8C19424; Sun, 1 Mar 2026 01:17:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772327863; bh=Gpp3g3wntO4Qc0y0xYsd/8EEdtn7INOVjn/nknEVZ/k=; h=From:To:Cc:Subject:Date:From; b=h0Z2SKvhaNxkRT9+hd1eb332niUyBcV4DXCK40ZEzP/dlldwW1yMcJjl1cHkOAqXc ftLNHgIXItjsV9KUuITFQApQarM3ri0G+Fn4Kl9999OtXpW5lyvloFKt8NhUwShn+r MdmOLw6/iPZNvkYFOxZi8FOr68zHEJrl+Ei4iOiqKjYTMvjrHFkCvtaDIyCsl6g3M+ wZbUXRPHoBmpMZomA7IL8FZoeTXMYfFeQPclyAEMEC7SH0XlMRxDTvItywtfxxCLvV HNObVfEV08PsPy2azIwQZYCp4gzOGRw8AIgqR6L/Oti5dPlf0aENWv+T5cZFh8W2LG oE+N4huj9yFDg== From: Sasha Levin To: stable@vger.kernel.org, imre.deak@intel.com Cc: Chaitanya Kumar Borah , Ankit Nautiyal , Joonas Lahtinen , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: FAILED: Patch "drm/i915/dp: Fix pipe BPP clamping due to HDR" failed to apply to 6.18-stable tree Date: Sat, 28 Feb 2026 20:17:41 -0500 Message-ID: <20260301011741.1671698-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.18-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From fe26ae6ac8b88fcdac5036b557c129a17fe520d2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 9 Feb 2026 15:38:16 +0200 Subject: [PATCH] drm/i915/dp: Fix pipe BPP clamping due to HDR The pipe BPP value shouldn't be set outside of the source's / sink's valid pipe BPP range, ensure this when increasing the minimum pipe BPP value to 30 due to HDR. While at it debug print if the HDR mode was requested for a connector by setting the corresponding HDR connector property. This indicates if the requested HDR mode could not be enabled, since the selected pipe BPP is below 30, due to a sink capability or link BW limit. v2: - Also handle the case where the sink could support the target 30 BPP only in DSC mode due to a BW limit, but the sink doesn't support DSC or 30 BPP as a DSC input BPP. (Chaitanya) - Debug print the connector's HDR mode in the link config dump, to indicate if a BPP >= 30 required by HDR couldn't be reached. (Ankit) - Add Closes: trailer. (Ankit) - Don't print the 30 BPP-outside of valid BPP range debug message if the min BPP is already > 30 (and so a target BPP >= 30 required for HDR is ensured). Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7052 Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15503 Fixes: ba49a4643cf53 ("drm/i915/dp: Set min_bpp limit to 30 in HDR mode") Cc: Chaitanya Kumar Borah Cc: # v6.18+ Reviewed-by: Ankit Nautiyal # v1 Reviewed-by: Chaitanya Kumar Borah Signed-off-by: Imre Deak Link: https://patch.msgid.link/20260209133817.395823-1-imre.deak@intel.com (cherry picked from commit 08b7ef16b6a03e8c966e286ee1ac608a6ffb3d4a) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e022c47e8ac2..e9f1ee1eafae7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2665,6 +2665,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits) { + struct intel_display *display = to_intel_display(intel_dp); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); struct intel_connector *connector = to_intel_connector(conn_state->connector); @@ -2677,8 +2678,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, limits->min_lane_count = intel_dp_min_lane_count(intel_dp); limits->max_lane_count = intel_dp_max_lane_count(intel_dp); - limits->pipe.min_bpp = intel_dp_in_hdr_mode(conn_state) ? 30 : - intel_dp_min_bpp(crtc_state->output_format); + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); if (is_mst) { /* * FIXME: If all the streams can't fit into the link with their @@ -2694,6 +2694,19 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, respect_downstream_limits); } + if (!dsc && intel_dp_in_hdr_mode(conn_state)) { + if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) && + limits->pipe.max_bpp >= 30) + limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30); + else + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Can't force 30 bpp for HDR (pipe bpp: %d-%d DSC-support: %s)\n", + connector->base.base.id, connector->base.name, + limits->pipe.min_bpp, limits->pipe.max_bpp, + str_yes_no(intel_dp_supports_dsc(intel_dp, connector, + crtc_state))); + } + if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) return false; @@ -2825,10 +2838,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, } drm_dbg_kms(display->drm, - "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", + "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " HDR %s link rate required %d available %d\n", pipe_config->lane_count, pipe_config->port_clock, pipe_config->pipe_bpp, FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), + str_yes_no(intel_dp_in_hdr_mode(conn_state)), intel_dp_config_required_rate(pipe_config), intel_dp_max_link_data_rate(intel_dp, pipe_config->port_clock, -- 2.51.0