From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9755430BA3; Sun, 1 Mar 2026 01:18:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772327924; cv=none; b=WjMFWWbIivbOx52z9hjT44CqWq6qepOgbwBnfYt/ePrpbku/kk8rP5B4fcllbolnbyi78nGEs45jHN+yfuSBLLpcIMOH+8hX11WpHid2GxrBrIUDkPjNrlzQC+/nsxusCQLRGt0BXuBRKgh4Pg3zuQT8QgD10eIG/5DEy7lWPHs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772327924; c=relaxed/simple; bh=J7nL2l1pFFeFXMVeZ1FKffbj2Mtyo0xsjmncKkXHccA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=s714EgEomyKj5HR+x9zhBRRi3fRsAdgAC2p9f1OCymQM0F5+wFev1rZRdNxCddj9hMvXBXyOnMtYY8MBxdF4nHrPFRCghthW9LX4Gz5Pj68YA97zJzQ7ij1UnPsIB+l1U9AlUXEgr8+fZ0jpAa0tMv6XDQOWPlyeIm9g/um9U44= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b3P79KI0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b3P79KI0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD7FEC19424; Sun, 1 Mar 2026 01:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772327923; bh=J7nL2l1pFFeFXMVeZ1FKffbj2Mtyo0xsjmncKkXHccA=; h=From:To:Cc:Subject:Date:From; b=b3P79KI0lS47lqgKFK/IXN2IKS7WbHanFfwoYmnvpAPn0qKboJQltp+in2t1tzVV7 SS/PCsq4w7o/ug66blwQFyINpp5tnaigvn18FFi2fCpmhDOkODzfzArrMd+DgwJegw zOsAdEeImEQSqJPjWmHIXG/KvLP+3azn0FaTNbIlZffnaIIMnyKiv/JqGwimxC4J7t YoL0dq7IqyNdq9ERBsXxZ8lNUpZ0iZ/UQb9cTdTP/qwtOljAlcid4a1RXCJMyUhBXc DEphpf3QAbAhBpOP+C8Kl4KHUfmn3pcv6uUjBk1AjX8hPRw7qbuWBKK+S/E2XY+FwL wXpKn3sTeHf0Q== From: Sasha Levin To: stable@vger.kernel.org, abelvesa@kernel.org Cc: Krzysztof Kozlowski , Bjorn Andersson , Abel Vesa , Vinod Koul , Bjorn, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: FAILED: Patch "dt-bindings: phy: qcom-edp: Add missing clock for X Elite" failed to apply to 6.12-stable tree Date: Sat, 28 Feb 2026 20:18:41 -0500 Message-ID: <20260301011841.1673141-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.12-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From 6b99eeacf6abb1ff2d6463c84e490343f39cf11a Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:53:27 +0200 Subject: [PATCH] dt-bindings: phy: qcom-edp: Add missing clock for X Elite On X Elite platform, the eDP PHY uses one more clock called ref. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So attach the this ref clock to the PHY. Cc: stable@vger.kernel.org # v6.10 Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-missing-refclk-v5-1-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index eb97181cbb957..bfc4d75f50ff9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -37,12 +37,15 @@ properties: - description: PLL register block clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 clock-names: + minItems: 2 items: - const: aux - const: cfg_ahb + - const: ref "#clock-cells": const: 1 @@ -64,6 +67,29 @@ required: - "#clock-cells" - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - qcom,x1e80100-dp-phy + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 + else: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + additionalProperties: false examples: -- 2.51.0