From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63CB5430BA3; Sun, 1 Mar 2026 01:23:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772328185; cv=none; b=iQsguMMN+K2FNVovZvOQ11pzspdh25UWhq4j5eg4vcA2nlDaJz3JeZI6GdlUNyquetxmXhJ5mnYznFOU5qA9B98kLk9EIEKwot24ZAUF2C1ssZtlHG7msWhhMs8UNzC2pxtwWtmVnBwFxOTB+LQh1qi25wihkQVv+rS1UbC2Hng= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772328185; c=relaxed/simple; bh=/LTe1+l48RFM1e2HNCEBDl0sKZ+EgZ8EXC3JPpMxWEc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=aU1mRchDFYjHX6r0oKQRNB+a2Z1vw4BZsFTgDz85dZ0dfSfAV1WqCBWNkAn8p0LPSdSVGXZyyYkCNW60RSKzaGl7WInDQmbkYUERddgkzzxJOBJ7dz+3g2uJOh/Nk3LUu4oHlevBbq30otbqxTl14n4Pa6kP9VxMriCrMp6lQF0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X7MDFNpf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X7MDFNpf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AEC8C19421; Sun, 1 Mar 2026 01:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772328184; bh=/LTe1+l48RFM1e2HNCEBDl0sKZ+EgZ8EXC3JPpMxWEc=; h=From:To:Cc:Subject:Date:From; b=X7MDFNpf5PFOO8DnXeLetow607jnmVv+6YIBgcthnkQqUy1A0SsksCaD+Pz6qSG97 YdJQRUDqZbXqWCkWaSY4OV96WM/U8xnqs0sj3PgVPWNRHx/c9QwgSx3E6ejl2CIvl7 skt3X0t3/uk0fIbkLld3JZ8yd78XKjljHgnB7u20eBkW0Z7wyNv+bDOJOylTyigpU0 krhJn3H7XMX4u4reUnodJOgrA4fLMGC/86E3DsGoSBaEbmSFEvkzp2Yw/2uEahS+YL 3Nb9PfwOWEyb4NMQ6+Z9/WH4C7Iy7h1n209vg0CkBRSQKyvhpR664E+aO+Q7L/7pO0 H8koYG+vs52Hg== From: Sasha Levin To: stable@vger.kernel.org, shawn.lin@rock-chips.com Cc: Andrew Powers-Holmes , Heiko Stuebner , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: FAILED: Patch "arm64: dts: rockchip: Fix rk356x PCIe range mappings" failed to apply to 6.12-stable tree Date: Sat, 28 Feb 2026 20:23:02 -0500 Message-ID: <20260301012303.1679675-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.12-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From f63ea193a404481f080ca2958f73e9f364682db9 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 5 Jan 2026 16:15:28 +0800 Subject: [PATCH] arm64: dts: rockchip: Fix rk356x PCIe range mappings The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so that there is no same address allocated from normal system memory. Otherwise it's broken if the same address assigned to the EP for DMA purpose.Fix it to sync with the vendor BSP. Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings") Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller") Cc: stable@vger.kernel.org Cc: Andrew Powers-Holmes Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1767600929-195341-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index e719a3df126c5..658097ed69714 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -185,7 +185,7 @@ pcie3x1: pcie@fe270000 { <0x0 0xf2000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -238,7 +238,7 @@ pcie3x2: pcie@fe280000 { <0x0 0xf0000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; + <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9ff..a2c4957a58992 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1022,7 +1022,7 @@ pcie2x1: pcie@fe260000 { power-domains = <&power RK3568_PD_PIPE>; ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; -- 2.51.0