From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 875E5386C1D for ; Mon, 2 Mar 2026 21:08:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772485704; cv=none; b=SUIi+hgSN0ZOShUcw0X64h4/8YhNDWn0049xBK5qlN66228b4CutkQz5vtby6pvJwxT0b42i9C9GYCbdRFGqAcz89bUo2Yr/qUx/iANHpw1YS+sTnOGom0aOQsktmzRH7IDGEa6CNFn48dS4PIPZdpR2WPSr4dnAVYoWPhiE6zE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772485704; c=relaxed/simple; bh=sdOwzxAPm5pwxrA5gG4pL0j7k+FvzYlobT6NNsTosaU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=o5B5a9Z7h4kUNJVhhMSUQbsTwFiutRJXAExcgJ1PR8k2W2nzz9srZIkvv45c22WraPSSnSOrit5BdtbJbTMf5p3n7uQBqrbwBKCtss5XeaGnNyNdpAze9L0AH0tUAsC2o/1tD2u+n5l+8nxp0z0oLaeO02Q2CunBT+TrhWx9Fcg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=vh2nBt+3; arc=none smtp.client-ip=95.215.58.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="vh2nBt+3" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1772485691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H2Cir8PjWMNKOAoAekYskevFXQhEA9TnJGz6taHG0ys=; b=vh2nBt+3A+Mr8CKxAum9hBKcSRfHzbir4dCXtTZt6RRSMbsUhV93o22EiqnDcixB7RFojP qAmnxy7s9NLrIYG6/oTs/Hh3wBINLNO3sUZ8YTro1efK9bonsVufXfD9VuaPD1hGIJKY5N aLDEiZD6rVfHhCDGr/CWRUz6lGn9G84= From: Matthew Schwartz To: Adrian Hunter , Ulf Hansson , Ben Chuang Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Schwartz , stable@vger.kernel.org Subject: [PATCH v2] mmc: sdhci-pci-gli: fix GL9750 DMA write corruption Date: Mon, 2 Mar 2026 13:07:17 -0800 Message-ID: <20260302210717.1159159-1-matthew.schwartz@linux.dev> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT The GL9750 SD host controller has intermittent data corruption during DMA write operations. The GM_BURST register's R_OSRC_Lmt field (bits 17:16), which limits outstanding DMA read requests from system memory, is not being cleared during initialization. The Windows driver sets R_OSRC_Lmt to zero, limiting requests to the smallest unit. Clear R_OSRC_Lmt to match the Windows driver behavior. This eliminates write corruption verified with f3write/f3read tests while maintaining DMA performance. Cc: stable@vger.kernel.org Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") Closes: https://lore.kernel.org/linux-mmc/33d12807-5c72-41ce-8679-57aa11831fad@linux.dev/ Acked-by: Adrian Hunter Signed-off-by: Matthew Schwartz --- Changes in v2: - Move GM_BURST register defines - Clear R_OSRC_Lmt in gli_set_9750 instead of gl9750_hw_setting to survive resets - Link to v1: https://lore.kernel.org/linux-mmc/20260227075909.3860183-1-matthew.schwartz@linux.dev/ Changes in v1: - Use the proper name for the register field - Link to RFC: https://lore.kernel.org/linux-mmc/20260117234800.931664-1-matthew.schwartz@linux.dev/ --- drivers/mmc/host/sdhci-pci-gli.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index b0f91cc9e40e4..6e4084407662a 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -68,6 +68,9 @@ #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) +#define SDHCI_GLI_9750_GM_BURST_SIZE 0x510 +#define SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT GENMASK(17, 16) + #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 @@ -345,10 +348,16 @@ static void gli_set_9750(struct sdhci_host *host) u32 misc_value; u32 parameter_value; u32 control_value; + u32 burst_value; u16 ctrl2; gl9750_wt_on(host); + /* clear R_OSRC_Lmt to avoid DMA write corruption */ + burst_value = sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE); + burst_value &= ~SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT; + sdhci_writel(host, burst_value, SDHCI_GLI_9750_GM_BURST_SIZE); + driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); -- 2.53.0