From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD67939280C for ; Mon, 9 Mar 2026 10:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053048; cv=none; b=rZjIead5U1yKjXrQa8tJdXLhTYYMqRr8NWwr9qZ/FpVRXqJO39np2M1xTR6uwEJ06IKtPK7xiwag+jAucZ7qqDeAxQTXLuIXVuIkE78rSlm8JtMoul6HaCQr9WTU0VbCyMMBQReyfUz+l0NscVLAwde31Fd9XL6ZpwLV/aGwq4c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053048; c=relaxed/simple; bh=6s2JzudWIB9fKiaz7X0wHZqAAo1bf94j5wi3KvALUa0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GvyxQyMbculJuJe6r2fxnSjF76cJksqQvX7J9HfErIGLR+N+/QijcZ7svvPexX7fXOBZz2qMjCNsPhIE7xZLKTgUJifjWxmcXTEKJlncyRPe03W7Auy6nxJSB6bqBryZWaEX2PUHEsOpHJbLUIJGpai4txbV/bBaCPdlvR6dzRg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IuTRD4Ww; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IuTRD4Ww" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A82C7C4CEF7; Mon, 9 Mar 2026 10:44:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773053048; bh=6s2JzudWIB9fKiaz7X0wHZqAAo1bf94j5wi3KvALUa0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IuTRD4WwhCusirodmCdkEEkdhqdqA1do+roSzYQQPOfRdpgE1ZoyRSRxVc0MsEYds lxKyz8axfKq+HIZujczN3Ir5jKMOxn5dYYDLWuc0CPV3oHmLsFARwrcZ1SvAFReC65 qGPNou1v9AAqVk0fNQdlbSf+tR+LvgIOFYWbDZDq8MCEETB/XK4+AeeEOx3tti47Od exqCf9kqdNK8e7onbUSNORX9IILz4HSR2/UA75GOi/PQBTbGVB3D9XbneehJoY75VZ wBM+iRNvvZ7Pl5sfr9AZQTiUCL104ZUr1MOsiyPm+S0XIHyWA14VIRTWDGHBlAJMDO rNo7dYO6pj/Ew== From: Sasha Levin To: stable@vger.kernel.org Cc: Kan Liang , "Peter Zijlstra (Intel)" , Eric Hu , Sasha Levin Subject: [PATCH 6.12.y 1/2] perf/x86/intel/uncore: Support more units on Granite Rapids Date: Mon, 9 Mar 2026 06:44:05 -0400 Message-ID: <20260309104406.795578-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2026030906-onion-junkyard-156b@gregkh> References: <2026030906-onion-junkyard-156b@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kan Liang [ Upstream commit 6d642735cdb6cdb814d2b6c81652caa53ce04842 ] The same CXL PMONs support is also avaiable on GNR. Apply spr_uncore_cxlcm and spr_uncore_cxldp to GNR as well. The other units were broken on early HW samples, so they were ignored in the early enabling patch. The issue has been fixed and verified on the later production HW. Add UPI, B2UPI, B2HOT, PCIEX16 and PCIEX8 for GNR. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Tested-by: Eric Hu Link: https://lkml.kernel.org/r/20250108143017.1793781-2-kan.liang@linux.intel.com Stable-dep-of: 6a8a48644c4b ("perf/x86/intel/uncore: Add per-scheduler IMC CAS count events") Signed-off-by: Sasha Levin --- arch/x86/events/intel/uncore_snbep.c | 48 ++++++++++++++++++---------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 543609d1231ef..76d96df1475a1 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6597,17 +6597,8 @@ void spr_uncore_mmio_init(void) /* GNR uncore support */ #define UNCORE_GNR_NUM_UNCORE_TYPES 23 -#define UNCORE_GNR_TYPE_15 15 -#define UNCORE_GNR_B2UPI 18 -#define UNCORE_GNR_TYPE_21 21 -#define UNCORE_GNR_TYPE_22 22 int gnr_uncore_units_ignore[] = { - UNCORE_SPR_UPI, - UNCORE_GNR_TYPE_15, - UNCORE_GNR_B2UPI, - UNCORE_GNR_TYPE_21, - UNCORE_GNR_TYPE_22, UNCORE_IGNORE_END }; @@ -6616,6 +6607,31 @@ static struct intel_uncore_type gnr_uncore_ubox = { .attr_update = uncore_alias_groups, }; +static struct intel_uncore_type gnr_uncore_pciex8 = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "pciex8", +}; + +static struct intel_uncore_type gnr_uncore_pciex16 = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "pciex16", +}; + +static struct intel_uncore_type gnr_uncore_upi = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "upi", +}; + +static struct intel_uncore_type gnr_uncore_b2upi = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "b2upi", +}; + +static struct intel_uncore_type gnr_uncore_b2hot = { + .name = "b2hot", + .attr_update = uncore_alias_groups, +}; + static struct intel_uncore_type gnr_uncore_b2cmi = { SPR_UNCORE_PCI_COMMON_FORMAT(), .name = "b2cmi", @@ -6640,21 +6656,21 @@ static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = { &gnr_uncore_ubox, &spr_uncore_imc, NULL, + &gnr_uncore_upi, NULL, NULL, NULL, + &spr_uncore_cxlcm, + &spr_uncore_cxldp, NULL, - NULL, - NULL, - NULL, - NULL, + &gnr_uncore_b2hot, &gnr_uncore_b2cmi, &gnr_uncore_b2cxl, - NULL, + &gnr_uncore_b2upi, NULL, &gnr_uncore_mdf_sbo, - NULL, - NULL, + &gnr_uncore_pciex16, + &gnr_uncore_pciex8, }; static struct freerunning_counters gnr_iio_freerunning[] = { -- 2.51.0