From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D04739280C for ; Mon, 9 Mar 2026 10:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053049; cv=none; b=Ezza20xzvO1VS3o6yt4PEkeO+1/Xe2CQf8UH4Wwuq/ELzeJeUMhC8lHfc3h1fAEPI4LnTnTYhr5uIHrASIEW608IKoB67WhV5yf3j7CiwRfy7ZoFXmYZg+7phuthOHALALauC/3pgODOpigtbbMBBqZ6RB1UMVkcSypfK0lQxPM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053049; c=relaxed/simple; bh=byKChppY0pg20bvPo2oZLSWFrOtLCVbHq3l0rsOXczY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u+h6X3yGkaS9yKcCY/aO5MW1sgJzzylNGWMZv3gNxgGLGWSfWo/ycY+yu5og+vuUXPEM/exlx12elWaGvg2NuEPCt1Fk88Ol+6dRlWe+RZSy/4BogpGuEFnA0FHLuB/iK7Y9bz3ORx0TsU4qgei+gkmdelHCkYhqnNOmvuk83dg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Et7bjnPv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Et7bjnPv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 830C6C19423; Mon, 9 Mar 2026 10:44:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773053049; bh=byKChppY0pg20bvPo2oZLSWFrOtLCVbHq3l0rsOXczY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Et7bjnPvJMiaBucQrvvnBGDaqbj5HKzATXdRQ14zPGnHXnBtQLuP619zaQ8+nz+LI JeHAjMBBBBizEBRA0x32IruHdiHWEPVCqjaQumkApHpSJgbiV50yLNcO2RwSFGnvP6 7EarCH2ti+DnW/O66UT9HGV64jtp6icIkMlIZ2DFYvSp+npj0CtItfv1lwKsueuFLj P7yd+QMAwjtausCY8EJHsxlcPsFi50RsvrVZKJCFAi+G1BhCpAwl1x5iw3QGgobEfx SBl7IsZyMsZz+g0BA2Y2kSLEPsqhnGJPU8q5tH2svIEkOMqnT+sWZZRFUDHVV784HE VL09/I9hSbMoA== From: Sasha Levin To: stable@vger.kernel.org Cc: Zide Chen , Reinette Chatre , "Peter Zijlstra (Intel)" , Dapeng Mi , Sasha Levin Subject: [PATCH 6.12.y 2/2] perf/x86/intel/uncore: Add per-scheduler IMC CAS count events Date: Mon, 9 Mar 2026 06:44:06 -0400 Message-ID: <20260309104406.795578-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260309104406.795578-1-sashal@kernel.org> References: <2026030906-onion-junkyard-156b@gregkh> <20260309104406.795578-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Zide Chen [ Upstream commit 6a8a48644c4b804123e59dbfc5d6cd29a0194046 ] IMC on SPR and EMR does not support sub-channels. In contrast, CPUs that use gnr_uncores[] (e.g. Granite Rapids and Sierra Forest) implement two command schedulers (SCH0/SCH1) per memory channel, providing logically independent command and data paths. Do not reuse the spr_uncore_imc[] configuration for these CPUs. Instead, introduce a dedicated gnr_uncore_imc[] with per-scheduler events, so userspace can monitor SCH0 and SCH1 independently. On these CPUs, replace cas_count_{read,write} with cas_count_{read,write}_sch{0,1}. This may break existing userspace that relies on cas_count_{read,write}, prompting it to switch to the per-scheduler events, as the legacy event reports only partial traffic (SCH0). Fixes: 632c4bf6d007 ("perf/x86/intel/uncore: Support Granite Rapids") Fixes: cb4a6ccf3583 ("perf/x86/intel/uncore: Support Sierra Forest and Grand Ridge") Reported-by: Reinette Chatre Signed-off-by: Zide Chen Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Dapeng Mi Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260210005225.20311-1-zide.chen@intel.com Signed-off-by: Sasha Levin --- arch/x86/events/intel/uncore_snbep.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 76d96df1475a1..c453ee7a52074 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6607,6 +6607,32 @@ static struct intel_uncore_type gnr_uncore_ubox = { .attr_update = uncore_alias_groups, }; +static struct uncore_event_desc gnr_uncore_imc_events[] = { + INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0, "event=0x05,umask=0xcf"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.scale, "6.103515625e-5"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.unit, "MiB"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1, "event=0x06,umask=0xcf"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.scale, "6.103515625e-5"), + INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.unit, "MiB"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0, "event=0x05,umask=0xf0"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.scale, "6.103515625e-5"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.unit, "MiB"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1, "event=0x06,umask=0xf0"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.scale, "6.103515625e-5"), + INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.unit, "MiB"), + { /* end: all zeroes */ }, +}; + +static struct intel_uncore_type gnr_uncore_imc = { + SPR_UNCORE_MMIO_COMMON_FORMAT(), + .name = "imc", + .fixed_ctr_bits = 48, + .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR, + .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL, + .event_descs = gnr_uncore_imc_events, +}; + static struct intel_uncore_type gnr_uncore_pciex8 = { SPR_UNCORE_PCI_COMMON_FORMAT(), .name = "pciex8", @@ -6654,7 +6680,7 @@ static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = { NULL, &spr_uncore_pcu, &gnr_uncore_ubox, - &spr_uncore_imc, + &gnr_uncore_imc, NULL, &gnr_uncore_upi, NULL, -- 2.51.0