From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E69D63859CC for ; Mon, 9 Mar 2026 11:38:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773056338; cv=none; b=qE32YhofYmIoL2+6nYiL+bekNAvs7BNMpuK9gGtiTXiELFHqleBFq4q4yzyHJiL5ytuhLcX00EppgsPRIhDjy5mZQE4m6e7Z8B/gZSoVGQhRJPBIZxMVyfYiW/sRUCgyVOIzLvx1VUX6IVnaDZg0omMgiXngabunYITsuQFc7iw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773056338; c=relaxed/simple; bh=x9tcDdGwLisCUL7UrxkRQS2OWni0pOimnhRo8u31MEE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h1gvhGbBuoPywocYFU05Kmrxm0ZGF7ukWPyOglItIH4Ajlx4ptG0rgRKbH8Fwps2rDm8HwftjT9qTeIgfXX7JR0Mlm00zE/fda5Sf3GzEKgYvJq5rINdvky/YMLzxNeN3REQ+Nmiy38EKNrj3KNdu1NC8rxE6W6LHmZGdAIulgQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vp+QtFza; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vp+QtFza" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB3F6C4CEF7; Mon, 9 Mar 2026 11:38:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773056337; bh=x9tcDdGwLisCUL7UrxkRQS2OWni0pOimnhRo8u31MEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vp+QtFzadS5ZfKzZ0CGUPpY/b9RG8E6eNqmKh0frERi8XCZ4J7XC6i0FHfORH2EOg fjFvJSCHIfTsSprGtgiNh3fqfijyMxlUb3aswE+OyKAhi4W3jJpF/zWTkTxjF4GwC3 kEKbC9tK+Fyp5+/VHsJspCkXNNAoUrT9BKCqysgMkTJlZPHXqJq3Nh0NC2aGOX/xQz g3aIq9rQFWLeyi/1l3UvTAB9ZUztJXcSavSclr8uhRASRAeujSKLlhv3WWRhYU74t2 /4eS4ZbLJ59d3pjUpDqYBc7YofOzcplRXayjI8luB47ivcdv/4RLitZDZwAQo8TJ5z DTnFmKTjJFA/w== From: Sasha Levin To: stable@vger.kernel.org Cc: Kim Phillips , "Borislav Petkov (AMD)" , Nikunj A Dadhania , Tom Lendacky , stable@kernel.org, Sasha Levin Subject: [PATCH 6.12.y] x86/sev: Allow IBPB-on-Entry feature for SNP guests Date: Mon, 9 Mar 2026 07:38:52 -0400 Message-ID: <20260309113852.824750-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2026030936-underrate-petty-47b7@gregkh> References: <2026030936-underrate-petty-47b7@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kim Phillips [ Upstream commit 9073428bb204d921ae15326bb7d4558d9d269aab ] The SEV-SNP IBPB-on-Entry feature does not require a guest-side implementation. It was added in Zen5 h/w, after the first SNP Zen implementation, and thus was not accounted for when the initial set of SNP features were added to the kernel. In its abundant precaution, commit 8c29f0165405 ("x86/sev: Add SEV-SNP guest feature negotiation support") included SEV_STATUS' IBPB-on-Entry bit as a reserved bit, thereby masking guests from using the feature. Allow guests to make use of IBPB-on-Entry when supported by the hypervisor, as the bit is now architecturally defined and safe to expose. Fixes: 8c29f0165405 ("x86/sev: Add SEV-SNP guest feature negotiation support") Signed-off-by: Kim Phillips Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky Cc: stable@kernel.org Link: https://patch.msgid.link/20260203222405.4065706-2-kim.phillips@amd.com [ merged missing SECURE_AVIC into RESERVED_BITS18_22 ] Signed-off-by: Sasha Levin --- arch/x86/boot/compressed/sev.c | 1 + arch/x86/coco/sev/core.c | 1 + arch/x86/include/asm/msr-index.h | 5 ++++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index a93e363388669..25601e65b387b 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -357,6 +357,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) MSR_AMD64_SNP_VMSA_REG_PROT | \ MSR_AMD64_SNP_RESERVED_BIT13 | \ MSR_AMD64_SNP_RESERVED_BIT15 | \ + MSR_AMD64_SNP_RESERVED_BITS18_22 | \ MSR_AMD64_SNP_RESERVED_MASK) /* diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index de1df0cb45dab..d5329211b1a7e 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -78,6 +78,7 @@ static const char * const sev_status_feat_names[] = { [MSR_AMD64_SNP_IBS_VIRT_BIT] = "IBSVirt", [MSR_AMD64_SNP_VMSA_REG_PROT_BIT] = "VMSARegProt", [MSR_AMD64_SNP_SMT_PROT_BIT] = "SMTProt", + [MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT] = "IBPBOnEntry", }; /* For early boot hypervisor communication in SEV-ES enabled guests */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b67280d761f63..7604161a77851 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -691,7 +691,10 @@ #define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT) #define MSR_AMD64_SNP_SMT_PROT_BIT 17 #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) -#define MSR_AMD64_SNP_RESV_BIT 18 +#define MSR_AMD64_SNP_RESERVED_BITS18_22 GENMASK_ULL(22, 18) +#define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT 23 +#define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT) +#define MSR_AMD64_SNP_RESV_BIT 24 #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f -- 2.51.0