From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDBD8318EE1; Thu, 12 Mar 2026 20:26:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773347173; cv=none; b=Xsa5kormGCPSdt2BegWM7brcKYZAaABJ1IYXadK9EaMHSIZ2E9d4PsasL9BJxSviThcJkkVP5qHY7oP/0mlTVBChkH+CaRYlzuPYXhhD12BN8Y2iVfctDyYNIVdqjXIn5Z2eFmHgykVUenGrRGhcWIAS8dn/J26/ZPp5lhIf1yI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773347173; c=relaxed/simple; bh=Hbxjy6/evVlNK/Oov39oU2nHgc2gGyZgG7rdAMizUME=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qESE5+oUNEIBtRmOF7uXQSO2Ri0uPdqW0f07hA9PUee3rt+1c4S2loWlyJq2AI0Arx4O2EBMk4UYiA7CSKjqCgb69yMMduK/5h3EPbG4BEAb5suTh6zBve75UWyMx5tBYR9xql/hgcq3rDG5OweuBL979OJMYrQ43omIwQ5Obbc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=jF3nVdbG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="jF3nVdbG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 411D8C4CEF7; Thu, 12 Mar 2026 20:26:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1773347173; bh=Hbxjy6/evVlNK/Oov39oU2nHgc2gGyZgG7rdAMizUME=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jF3nVdbGDnmBn5H0ev0XqWAsOc/PDAQXHvSeSGn84a3uPRY2fRlCl2UBx6ZUE+sCE b7bT+xNlrCEV3RBiA/Xz/gTv01L8HiPzrsPtyu4R2F2oOP0VQMebnGc8vwAK7QJv2i B1eigGObaOhTNBlzpq3aLMyABBmUMKyf7OuB2WSY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Guruvendra Punugupati , Raju Rangoju , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.12 192/265] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds Date: Thu, 12 Mar 2026 21:09:39 +0100 Message-ID: <20260312201025.250792177@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260312201018.128816016@linuxfoundation.org> References: <20260312201018.128816016@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Raju Rangoju [ Upstream commit 9439a661c2e80485406ce2c90b107ca17858382d ] Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits to 3 bits to properly support all speed settings. The MAC_TCR register's SS field encoding requires 3 bits to represent all supported speeds: - 0x00: 10Gbps (XGMII) - 0x02: 2.5Gbps (GMII) / 100Mbps - 0x03: 1Gbps / 10Mbps - 0x06: 2.5Gbps (XGMII) - P100a only With only 2 bits, values 0x04-0x07 cannot be represented, which breaks 2.5G XGMII mode on newer platforms and causes incorrect speed select values to be programmed. Fixes: 07445f3c7ca1 ("amd-xgbe: Add support for 10 Mbps speed") Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Raju Rangoju Link: https://patch.msgid.link/20260226170753.250312-1-Raju.Rangoju@amd.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/amd/xgbe/xgbe-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h index aa25a8a0a106f..d99d2295eab0f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h @@ -514,7 +514,7 @@ #define MAC_SSIR_SSINC_INDEX 16 #define MAC_SSIR_SSINC_WIDTH 8 #define MAC_TCR_SS_INDEX 29 -#define MAC_TCR_SS_WIDTH 2 +#define MAC_TCR_SS_WIDTH 3 #define MAC_TCR_TE_INDEX 0 #define MAC_TCR_TE_WIDTH 1 #define MAC_TCR_VNE_INDEX 24 -- 2.51.0