From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D509333554F for ; Mon, 16 Mar 2026 16:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773679378; cv=none; b=c4rrAQFpWlX1p4iKfA6By1kH+ACoF0psUWMZsL4EvvFL6er6omW/wzH1mJCuQIE/57u0aK0OWWYkRVw4ewDBTPagx5cndqqynHX1rM/rYr+lDuWhYTr5FESE/4UGqXWLNKjEulyXZ0Er/t+FmcfDV19LNxgh1JYYZJ43lG6DV3g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773679378; c=relaxed/simple; bh=kzwLdOOW8mowfFnSs6OLMxZEQWaIBm+6BS9qFkd4LhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MY+fMG+0YZiGnSkEiOCzQ+l9Lyl56akBoteue84R5Qp+nICvSuOTR8FS/0Rj0QWLgUM+haOOjRev7hpWM29l7zTLF6cRa67mz2XhEr0GFcALs1bEK4BZTuHybdu/jes+QnkdrnioF1/Q2BS02Wo1b1cDjGqYJoDfMDpVxQBtbBY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U4H8R2CH; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U4H8R2CH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773679377; x=1805215377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kzwLdOOW8mowfFnSs6OLMxZEQWaIBm+6BS9qFkd4LhY=; b=U4H8R2CH+LNgQ6Ctt7NgwO6sDn1Fvrk49EGKZy2p5cq2P6zbl6eS/HjD lp3tiA6klp97i62nXlAVV6K//7oNgLXrhWH8QT2a3SJkndCqQm5cm0DRL ZhUFArtpLAWcvtIb7uw6bw0MadHdzQNrr9EnGLiAPFqcU57K4Ei1hexiI +EkyLF/lQiXDYe1Rn+Je2msFA2X155UINN5yQKNbFWrGjXT2tDyfUQwyn QVWFhes+LYjI5XoaCdcB3N9B27663AZxsOCPjYczp+55qspUC8tclDcXM /fJkAQv/PU7a8YtY9Pad3xjoiQtj9rCwDa2hYIJ9At1Dac+7ZwEyf/oYB w==; X-CSE-ConnectionGUID: ND/7cXCWTlae4k+iKz5KDw== X-CSE-MsgGUID: pYgchtcRRAKN1QH6Eh1hOA== X-IronPort-AV: E=McAfee;i="6800,10657,11731"; a="97308778" X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="97308778" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 09:42:57 -0700 X-CSE-ConnectionGUID: da5GKcQNRLOdNepK+ODK6w== X-CSE-MsgGUID: pFSUFvd+RTiLcI3vBxtp2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="221013860" Received: from dut6094bmgfrd.fm.intel.com ([10.80.55.31]) by orviesa006.jf.intel.com with ESMTP; 16 Mar 2026 09:42:57 -0700 From: Jia Yao To: intel-xe@lists.freedesktop.org Cc: Jia Yao , stable@vger.kernel.org, Shuicheng Lin , Mathew Alwin , Michal Mrozek , Matthew Brost , Matthew Auld , =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Subject: [PATCH v6 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Date: Mon, 16 Mar 2026 16:42:52 +0000 Message-ID: <20260316164253.262406-2-jia.yao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316164253.262406-1-jia.yao@intel.com> References: <20260129000147.339361-1-jia.yao@intel.com> <20260316164253.262406-1-jia.yao@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add validation in xe_vm_madvise_ioctl() to reject PAT indices with XE_COH_NONE coherency mode when applied to CPU cached memory. Using coh_none with CPU cached buffers is a security issue. When the kernel clears pages before reallocation, the clear operation stays in CPU cache (dirty). GPU with coh_none can bypass CPU caches and read stale sensitive data directly from DRAM, potentially leaking data from previously freed pages of other processes. This aligns with the existing validation in vm_bind path (xe_vm_bind_ioctl_validate_bo). v2(Matthew brost) - Add fixes - Move one debug print to better place v3(Matthew Auld) - Should be drm/xe/uapi - More Cc v4(Shuicheng Lin) - Fix kmem leak issues by the way v5 - Remove kmem leak because it has been merged by another patch v6 - Remove the fix which is not related to current fix Fixes: ada7486c5668 ("drm/xe: Implement madvise ioctl for xe") Cc: stable@vger.kernel.org # v6.18 Cc: Shuicheng Lin Cc: Mathew Alwin Cc: Michal Mrozek Cc: Matthew Brost Cc: Matthew Auld Signed-off-by: Jia Yao Reviewed-by: Matthew Auld Acked-by: Michal Mrozek Acked-by: José Roberto de Souza --- drivers/gpu/drm/xe/xe_vm_madvise.c | 45 ++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c index 869db304d96d..f26eb86e9c47 100644 --- a/drivers/gpu/drm/xe/xe_vm_madvise.c +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c @@ -365,6 +365,43 @@ static void xe_madvise_details_fini(struct xe_madvise_details *details) drm_pagemap_put(details->dpagemap); } +static bool check_pat_args_are_sane(struct xe_device *xe, + struct xe_vmas_in_madvise_range *madvise_range, + u16 pat_index) +{ + u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); + int i; + + /* + * Using coh_none with CPU cached buffers is not allowed. + * Otherwise CPU page clearing can be bypassed, which is a + * security issue. GPU can directly access system memory and + * bypass CPU caches, potentially reading stale sensitive data + * from previously freed pages. + */ + if (coh_mode != XE_COH_NONE) + return true; + + for (i = 0; i < madvise_range->num_vmas; i++) { + struct xe_vma *vma = madvise_range->vmas[i]; + struct xe_bo *bo = xe_vma_bo(vma); + + if (bo) { + /* BO with WB caching + COH_NONE is not allowed */ + if (XE_IOCTL_DBG(xe, bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) + return false; + /* Imported dma-buf without caching info, assume cached */ + if (XE_IOCTL_DBG(xe, !bo->cpu_caching)) + return false; + } else if (XE_IOCTL_DBG(xe, xe_vma_is_cpu_addr_mirror(vma) || + xe_vma_is_userptr(vma))) + /* System memory (userptr/SVM) is always CPU cached */ + return false; + } + + return true; +} + static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas, int num_vmas, u32 atomic_val) { @@ -455,6 +492,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil if (err || !madvise_range.num_vmas) goto madv_fini; + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) { + if (!check_pat_args_are_sane(xe, &madvise_range, + args->pat_index.val)) { + err = -EINVAL; + goto free_vmas; + } + } + if (madvise_range.has_bo_vmas) { if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) { if (!check_bo_args_are_sane(vm, madvise_range.vmas, -- 2.43.0