From: Jia Yao <jia.yao@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Jia Yao <jia.yao@intel.com>,
stable@vger.kernel.org, Shuicheng Lin <shuicheng.lin@intel.com>,
Mathew Alwin <alwin.mathew@intel.com>,
Michal Mrozek <michal.mrozek@intel.com>,
Matthew Brost <matthew.brost@intel.com>,
Matthew Auld <matthew.auld@intel.com>
Subject: [PATCH v6 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR
Date: Mon, 16 Mar 2026 16:42:53 +0000 [thread overview]
Message-ID: <20260316164253.262406-3-jia.yao@intel.com> (raw)
In-Reply-To: <20260316164253.262406-1-jia.yao@intel.com>
Add validation in xe_vm_bind_ioctl() to reject PAT indices with
XE_COH_NONE coherency mode when used with
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR, consistent with the existing
validation for DRM_XE_VM_BIND_OP_MAP_USERPTR.
CPU address mirror mappings use system memory which is CPU cached,
making them incompatible with COH_NONE PAT index. Using COH_NONE with
CPU cached buffers is a security issue: GPU can bypass CPU caches and
directly read stale sensitive data from DRAM, potentially leaking data
from previously freed pages.
Although CPU_ADDR_MIRROR mappings don't create actual memory mappings
(the range is reserved for dynamic mapping on GPU page faults), the
underlying system memory is still CPU cached, so the same PAT coherency
restrictions as MAP_USERPTR should apply.
v2:
- Correct fix tag
Fixes: e1fbc4f18d5b ("drm/xe/uapi: support pat_index selection with vm_bind")
Cc: stable@vger.kernel.org # v6.18
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Mathew Alwin <alwin.mathew@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_vm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 5572e12c2a7e..1c4b4a5eeadb 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3491,7 +3491,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
XE_IOCTL_DBG(xe, obj &&
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
- op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
+ (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || is_cpu_addr_mirror)) ||
XE_IOCTL_DBG(xe, comp_en &&
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
--
2.43.0
next prev parent reply other threads:[~2026-03-16 16:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260129000147.339361-1-jia.yao@intel.com>
2026-01-30 22:07 ` [PATCH v3] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-02-03 2:54 ` Lin, Shuicheng
2026-02-04 15:13 ` Souza, Jose
2026-02-03 15:48 ` [PATCH v4] " Jia Yao
2026-02-03 16:38 ` Matthew Auld
2026-02-03 16:59 ` Yao, Jia
2026-03-10 14:50 ` Mrozek, Michal
2026-03-16 7:22 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and Jia Yao
2026-03-16 7:22 ` [PATCH v5 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 10:59 ` Matthew Auld
2026-03-16 15:29 ` Lin, Shuicheng
2026-03-16 7:22 ` [PATCH v5 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-16 11:40 ` Matthew Auld
2026-03-16 16:42 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-16 16:42 ` [PATCH v6 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 16:42 ` Jia Yao [this message]
2026-03-17 10:45 ` [PATCH v6 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Matthew Auld
2026-03-19 11:58 ` [PATCH v7 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-19 11:58 ` [PATCH v7 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-19 11:58 ` [PATCH v7 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
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