From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 721413254A9 for ; Mon, 16 Mar 2026 19:18:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773688727; cv=none; b=NShBZbutTW6aREgVkCeUE/qZ1H3lN+E49fc0L+OUUs4SXV96FJL4UH0oztY20p4R7Ti2xM1ef5BddxIXdctEZODOc00761QWndMDmMi/AggVPq/z1AHfnUchADMlLeM4cGZrNxwjaY8BwcEMeA2PWz/7fZmvF4BufxAp3WHo8bs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773688727; c=relaxed/simple; bh=xtpKpCpWSd6aM1vr5PBkuAWV7Bj79kWQ9bc1/QOAvfA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RX1XhrnAa5uSnLMcogVPcUAYKKSexXXYuvkMbbO3GNuMAbqd4EPeDv5nmWbRjoQ2f5qdT1uEE/S7jYrfrziexWzPBbkpyqT1N9o3RbCrvk8YnEGAUeDfmY7ECG/ul3i5dMKFVPAihauUAzAKPfjDgMyqL8U1iVVvlwl1BHi/rlQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tT5NgvCj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tT5NgvCj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F2A1C19421; Mon, 16 Mar 2026 19:18:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773688727; bh=xtpKpCpWSd6aM1vr5PBkuAWV7Bj79kWQ9bc1/QOAvfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tT5NgvCjl6aNkvdqviLVJJN0VGt2n74YdJINHCHpFPP5YVpESOmIQa+2HNW3+qBdr gprpuEOnVkHdFJgAhUBHOeuWB8K/cVgV5x13BhoF5qup4UrBW7kmq1rrNGzK4EBSL5 1fbaW83AQkTUVWjPaXP8gdfiOvCtNdjcRi1Z4REtR36kHlSoA+wzBWYX+4HNudwTXr Q7qYnzXkEQr1eui/AKVXGSDOErzxQTBf023D/97KVvRmYQKIrBaCLTq583vGreUIJw fY1svdtLS5ymI0q5vREujIjfTl9ZKQR5kEjT7owQcW0Wsf5BIK2cY0Gdx109Ep68Z0 2dnGs5/b/V1hQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Naveen N Rao , Sean Christopherson , Sasha Levin Subject: [PATCH 6.12.y 1/3] KVM: SVM: Limit AVIC physical max index based on configured max_vcpu_ids Date: Mon, 16 Mar 2026 15:18:43 -0400 Message-ID: <20260316191845.1350980-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2026031633-gambling-shock-b6ca@gregkh> References: <2026031633-gambling-shock-b6ca@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Naveen N Rao [ Upstream commit 574ef752d4aea04134bc121294d717f4422c2755 ] KVM allows VMMs to specify the maximum possible APIC ID for a virtual machine through KVM_CAP_MAX_VCPU_ID capability so as to limit data structures related to APIC/x2APIC. Utilize the same to set the AVIC physical max index in the VMCB, similar to VMX. This helps hardware limit the number of entries to be scanned in the physical APIC ID table speeding up IPI broadcasts for virtual machines with smaller number of vCPUs. Unlike VMX, SVM AVIC requires a single page to be allocated for the Physical APIC ID table and the Logical APIC ID table, so retain the existing approach of allocating those during VM init. Signed-off-by: Naveen N Rao (AMD) Link: https://lore.kernel.org/r/adb07ccdb3394cd79cb372ba6bcc69a4e4d4ef54.1757009416.git.naveen@kernel.org Signed-off-by: Sean Christopherson Stable-dep-of: 87d0f901a9bd ("KVM: SVM: Set/clear CR8 write interception when AVIC is (de)activated") Signed-off-by: Sasha Levin --- arch/x86/kvm/svm/avic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 63dea8ecd7efc..50e49558a2c99 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -85,6 +85,7 @@ struct amd_svm_iommu_ir { static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb = svm->vmcb01.ptr; + struct kvm *kvm = svm->vcpu.kvm; vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; @@ -100,7 +101,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |= X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |= X2AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= min(kvm->arch.max_vcpu_ids - 1, + X2AVIC_MAX_PHYSICAL_ID); /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -111,7 +113,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= min(kvm->arch.max_vcpu_ids - 1, + AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } -- 2.51.0