From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6187728E00 for ; Tue, 17 Mar 2026 12:17:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773749841; cv=none; b=Ccx47vT5oW8yZUNqEWrN3RC3rj3JC4c0nJR0TAbTTJ2lMsx8C+Uai2I5ACqKRiMDAqR/M6nFDDsZGo9amvPVmZFEPoDP0AiTsuAaj38W0i5oLD87fNNrVkA5PtS9jAvLpX8WQQphRY9FjM62rhmDwZ/tFt3Kw9+J6CMnvDkUO9I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773749841; c=relaxed/simple; bh=9uRl5U3jU5QiKIKO5y/qljmAC2hT1l0MsJC11CbM5Gc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fmemAFV6uiDqZfMmXOonqi1TRx8VY/0k4wVJ26FfSwfc28QwcUOcdLnvdVH0wuRMKsY/zbSU2vGhqwBLJpkAcxrZss+uExNmq6QQYduCrS0j/U1YVldHkvlZSXFbGr7zJP/ivBHqG8+dulxCmxW3CkkTofYl092ul+r3xeup1Cc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fgJGRbQE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fgJGRbQE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF16DC19425; Tue, 17 Mar 2026 12:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773749841; bh=9uRl5U3jU5QiKIKO5y/qljmAC2hT1l0MsJC11CbM5Gc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fgJGRbQEPZ/VhvFZDbKBNNtDuqoPZTMoFj8/nS9enXO0XNmphFrRxElW2b2uUwdrQ XV3iLpYiA6NlEArMKNWjhVf/exd5idRF8gOC+uhuq/KezCdxFkjN6cSwBPmowpYUXt AMkXESagP2OEZlKSw88C5YBKcxjKV+BbcTDd8cQ7NAyEWc32zd/FxEuY+aAkf9Mzec JCRpAVy0gyIZUNouOk55FyVvXnWts/S1XgYxLEbmJeAZZ8Ew7KYhlmxNKIyirU+h2M 4sQBL6j/DAHlotSonbaxPrw1L12jsKwXANjLgSxOzpB3mywdKgMbscuJQyQbF5TvNh f+b895yo+WYBg== From: Sasha Levin To: stable@vger.kernel.org Cc: Shawn Lin , Ulf Hansson , Sasha Levin Subject: [PATCH 6.12.y 2/3] mmc: dw_mmc-rockchip: Add memory clock auto-gating support Date: Tue, 17 Mar 2026 08:17:17 -0400 Message-ID: <20260317121718.140381-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260317121718.140381-1-sashal@kernel.org> References: <2026031758-blob-blot-0711@gregkh> <20260317121718.140381-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Shawn Lin [ Upstream commit ff6f0286c896f062853552097220dd93961be9c4 ] Per design recommendations, the memory clock can be gated when there is no in-flight transfer, which helps save power. This feature is introduced alongside internal phase support, and this patch enables it. Signed-off-by: Shawn Lin Signed-off-by: Ulf Hansson Stable-dep-of: 6465a8bbb0f6 ("mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support") Signed-off-by: Sasha Levin --- drivers/mmc/host/dw_mmc-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 9b17490554d7d..3d1ec1ced6f62 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -18,6 +18,8 @@ #define RK3288_CLKGEN_DIV 2 #define SDMMC_TIMING_CON0 0x130 #define SDMMC_TIMING_CON1 0x134 +#define SDMMC_MISC_CON 0x138 +#define MEM_CLK_AUTOGATE_ENABLE BIT(5) #define ROCKCHIP_MMC_DELAY_SEL BIT(10) #define ROCKCHIP_MMC_DEGREE_MASK 0x3 #define ROCKCHIP_MMC_DEGREE_OFFSET 1 @@ -469,6 +471,7 @@ static int dw_mci_rk3576_parse_dt(struct dw_mci *host) static int dw_mci_rockchip_init(struct dw_mci *host) { + struct dw_mci_rockchip_priv_data *priv = host->priv; int ret, i; /* It is slot 8 on Rockchip SoCs */ @@ -493,6 +496,9 @@ static int dw_mci_rockchip_init(struct dw_mci *host) dev_warn(host->dev, "no valid minimum freq: %d\n", ret); } + if (priv->internal_phase) + mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); + return 0; } -- 2.51.0