From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CDCA3BED6B for ; Tue, 17 Mar 2026 12:17:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773749842; cv=none; b=EnkiI+E9+2A6dfbXyN6rW+9OwBS6FuCHegxS0c3GZJ3UAMesKncugco1c8Q74qLFvg9tb5IccDpS6X3dot2wIudlIiGiquWzRtFV31vYUE2u6k2OKCLr4+FOyGxvgk17kqiRjZXHdPA/4NgTr8sCLU4kMni0NMGLsiBjA83rnBU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773749842; c=relaxed/simple; bh=1Z4GS4lJbDXXwBgqV6z7L2NltcHBw+BKc5biTqm37Zs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qz/CABZHyCOHyyPQb+DkSqmoB+8WGrBEjEWtqJX47LvVOKFBxLMLGk2CM9lmRK4t0RzFK4Lawl8MBTdJObL5I90IDnHoosYhW60+ELJCcxd8igM0t+4Qx55KBKDKFi0dbFGE5V6eCS1y5a8PH/Gaf1E9LbIxNrn84iu3aRc4yw4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mQVN3Zjs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mQVN3Zjs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A6B7C4CEF7; Tue, 17 Mar 2026 12:17:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773749842; bh=1Z4GS4lJbDXXwBgqV6z7L2NltcHBw+BKc5biTqm37Zs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mQVN3ZjsyQtfK8CJJuCBKtz2PVh6DD23VqcLGceWP9vE5kwP/v2C7vrWm7yqXs9BU PIaffT0CaDNKxiJzcJbEYfDd3CDOO4JX6seYzVd0sW8kYpill1c+nuEPnMx9pvdo4i dQdRBR3BPUecX7VrKt07BYvhTfUGKpwR/KL9GomXbtSFTPYnrpUIuITrtHaae9EsYt 94IgyC9JE2ObFv78MLcjEh6FjmKI6Ca9fzsYvA055+wvPYr+BjiNuLSrl9AYEOG3L/ sXIrZJVji79sjo0NG9l6lB3TMMXI676ncmjtOQyJuwDIq4IPdK9AiA0N6+qThz5Yn6 W63hJAzJMO0PQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Shawn Lin , Marco Schirrmeister , Heiko Stuebner , Ulf Hansson , Sasha Levin Subject: [PATCH 6.12.y 3/3] mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support Date: Tue, 17 Mar 2026 08:17:18 -0400 Message-ID: <20260317121718.140381-3-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260317121718.140381-1-sashal@kernel.org> References: <2026031758-blob-blot-0711@gregkh> <20260317121718.140381-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Shawn Lin [ Upstream commit 6465a8bbb0f6ad98aeb66dc9ea19c32c193a610b ] RK3576 is the first platform to introduce internal phase support, and subsequent platforms are expected to adopt a similar design. In this architecture, runtime suspend powers off the attached power domain, which resets registers, including vendor-specific ones such as SDMMC_TIMING_CON0, SDMMC_TIMING_CON1, and SDMMC_MISC_CON. These registers must be saved and restored, a requirement that falls outside the scope of the dw_mmc core. Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support") Signed-off-by: Shawn Lin Tested-by: Marco Schirrmeister Reviewed-by: Heiko Stuebner Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/dw_mmc-rockchip.c | 38 +++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 3d1ec1ced6f62..ec72453203de2 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -37,6 +37,8 @@ struct dw_mci_rockchip_priv_data { int default_sample_phase; int num_phases; bool internal_phase; + int sample_phase; + int drv_phase; }; /* @@ -573,9 +575,43 @@ static void dw_mci_rockchip_remove(struct platform_device *pdev) dw_mci_pltfm_remove(pdev); } +static int dw_mci_rockchip_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct dw_mci *host = platform_get_drvdata(pdev); + struct dw_mci_rockchip_priv_data *priv = host->priv; + + if (priv->internal_phase) { + priv->sample_phase = rockchip_mmc_get_phase(host, true); + priv->drv_phase = rockchip_mmc_get_phase(host, false); + } + + return dw_mci_runtime_suspend(dev); +} + +static int dw_mci_rockchip_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct dw_mci *host = platform_get_drvdata(pdev); + struct dw_mci_rockchip_priv_data *priv = host->priv; + int ret; + + ret = dw_mci_runtime_resume(dev); + if (ret) + return ret; + + if (priv->internal_phase) { + rockchip_mmc_set_phase(host, true, priv->sample_phase); + rockchip_mmc_set_phase(host, false, priv->drv_phase); + mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); + } + + return ret; +} + static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) - RUNTIME_PM_OPS(dw_mci_runtime_suspend, dw_mci_runtime_resume, NULL) + RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL) }; static struct platform_driver dw_mci_rockchip_pltfm_driver = { -- 2.51.0