From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F161414F70 for ; Tue, 17 Mar 2026 16:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773765570; cv=none; b=M3J3fZGpop2NUrXtHYcwW98tLfiqO+C3xL9K0ckrFMKX7ZXMwf3tFtZmDEIERDP6ZjJbP2gpSgmeH7Ypw8yPV/UpnTU55bmjgqbpWU+fc7IDXp31iO3pvDRAFSDWlBgyBzUu519xDtHZfOen1zzsBovAGaODq/gOCkPwntp9n7c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773765570; c=relaxed/simple; bh=lG3D3Y2Z7iNjZaNfg+rqkA5wSyunmmcMamSLFiAeTzI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nuT3yBX6kW8ZUxdbmkDNHMLCf2UBv5MI+42dF+uF5duLjqkkcwus9TD99MkSyg8Y98WHb4qC0qyZOyNjyz/iHPVY3AgpuiQ2T+eftzcyLlZDSNPxyvXBweV7+ZWog2ksz6gOpwdybDXydvF0ZPXP9a67+l6Cv+vN5OPDK2jHzxE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h/ZmzK6Z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h/ZmzK6Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5493CC2BCAF; Tue, 17 Mar 2026 16:39:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773765569; bh=lG3D3Y2Z7iNjZaNfg+rqkA5wSyunmmcMamSLFiAeTzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h/ZmzK6ZCkdMX82p3Dl2ge/vdT65SyxOEWb/FpljZrYMtk3If/SxPGTa/InaGZo6R V27aAcjT7w1EijeqJUkBfHP4goc8NZ0Y1d/oXiO3zY8r2g9h2E0EH2rNflHcJbyZNb K1uv962N/tkCOJcQx+dOY3pBVafoMV+2a/AqGfxLQvHGmIkpf8kVeZ1Sxpph64hFny GRT5cCvKBzCEMqzDB6/PnfToqRjs28byEir/+LpnrKotAZ+d4iesnfps04YOmH6rfb WFziEkWHSszjRy9NVLZSVuP2pyJQAWj/hV4UDqS+WDUgliWaRcYgP1L0Y53hfMya5h AOv0WtyQHEiWg== From: Sasha Levin To: stable@vger.kernel.org Cc: Animesh Manna , =?UTF-8?q?Jouni=20H=C3=B6gander?= , Sasha Levin Subject: [PATCH 6.12.y 4/8] drm/i915/lobf: Add lobf enablement in post plane update Date: Tue, 17 Mar 2026 12:39:20 -0400 Message-ID: <20260317163924.220634-4-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260317163924.220634-1-sashal@kernel.org> References: <2026031731-secret-rocket-af05@gregkh> <20260317163924.220634-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Animesh Manna [ Upstream commit 172757acd6f60625f09760ef0ffdcac01d8ed58a ] Enablement of LOBF is added in post plane update whenever has_lobf flag is set. As LOBF can be enabled in non-psr case as well so adding in post plane update. There is no change of configuring alpm with psr path. v1: Initial version. v2: Use encoder-mask to find the associated encoder from crtc-state. [Jani] v3: Remove alpm_configure from intel_psr.c. [Jouni] Signed-off-by: Animesh Manna Reviewed-by: Jouni Högander Link: https://lore.kernel.org/r/20250423092334.2294483-3-animesh.manna@intel.com Stable-dep-of: eb4a7139e973 ("drm/i915/alpm: ALPM disable fixes") Signed-off-by: Sasha Levin --- drivers/gpu/drm/i915/display/intel_alpm.c | 25 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 4 ++++ drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 57afb25191bd9..d256bb831b136 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -365,6 +365,31 @@ void intel_alpm_configure(struct intel_dp *intel_dp, lnl_alpm_configure(intel_dp, crtc_state); } +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_encoder *encoder; + + if (!crtc_state->has_lobf && !crtc_state->has_psr) + return; + + for_each_intel_encoder_mask(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp; + + if (!intel_encoder_is_dp(encoder)) + continue; + + intel_dp = enc_to_intel_dp(encoder); + + if (intel_dp_is_edp(intel_dp)) + intel_alpm_configure(intel_dp, crtc_state); + } +} + static int i915_edp_lobf_info_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 8c409b10dce6c..2f862b0476a8a 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -12,6 +12,8 @@ struct intel_dp; struct intel_crtc_state; struct drm_connector_state; struct intel_connector; +struct intel_atomic_state; +struct intel_crtc; void intel_alpm_init_dpcd(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, @@ -21,6 +23,8 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct drm_connector_state *conn_state); void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp); bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e2736f50fef83..bb05c8fd5e5f3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -57,6 +57,7 @@ #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "i9xx_wm.h" +#include "intel_alpm.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_audio.h" @@ -1116,6 +1117,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + intel_alpm_post_plane_update(state, crtc); + intel_psr_post_plane_update(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 16fd393de04fc..855f22f1f8328 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1886,9 +1886,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_dp->psr.psr2_sel_fetch_enabled ? IGNORE_PSR2_HW_TRACKING : 0); - if (intel_dp_is_edp(intel_dp)) - intel_alpm_configure(intel_dp, crtc_state); - /* * Wa_16013835468 * Wa_14015648006 -- 2.51.0