From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF2D82D9EF4 for ; Thu, 19 Mar 2026 13:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773928096; cv=none; b=J9snAwgp1jjU/MhRA2UI0kvEdON7wCBzbSS32W6OLKnePfeUKG11Gq4TLA7MZi2Xnc7CSeeZ62SBUGSDesDm0wnFMZUwIFl/Wq6XhOC4xAseZ4Ii5osfDFKQ25LNHm8lmdgfCywTOsjIYhFIYJif2wpcmdHS1pLmuBSe1zWJ9ME= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773928096; c=relaxed/simple; bh=U3N+jiUeFRP89MRT0uGBZjsMgO1qbzRVLBUglrc7w7I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DezNoAkJ1SloH09r/M9J9fqlph1PO+bLFvFlRD5N+P14zNdyliMqHL3JHQVAdEjaEi6WyuGYfSsVSzIOfy10Qsg58hInchse/vhrK3kp1JVdI9JrUteO6WHMCBRoi0+pblY1M7vf5fWtWgRgX1Tm91fdW2KXifweN48YYk+mTog= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XWqvX46J; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XWqvX46J" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773928094; x=1805464094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U3N+jiUeFRP89MRT0uGBZjsMgO1qbzRVLBUglrc7w7I=; b=XWqvX46JzGwxQaC3/XC4lT2rgmCgq8jTYFdC0aGy76MYCkIulGnfCHR9 IqRdCUqE1PSBjlA6XFN168v5r28I3Ppnq4Uj2iEeY+4aoyg18I3w0RGg6 bjqACF9Ws3K8HHLIyB60LiVgVgbtsTxtaf+O/rbP1G7StpTmIFnKBkj+x /lQFb2vIA5JWUqXFRDuSB52PVBnxZ66PI/1OsvK0+1YcY5wIoJD9pyR/G cNLJ5710acLWPYYBOhNvlFMf74nTSYGglcyqgCck2Uo4PEwMKpY+gq2AH VBDJcnla1Xuvg9Ze3QbHX1iWKbg5Xt2HwII1qX4W0RAg7fuDZVwybR8sv g==; X-CSE-ConnectionGUID: wZ6tQ4gPTwWefKFNWLBfBA== X-CSE-MsgGUID: wQlip0umQL+qKosZTFGruQ== X-IronPort-AV: E=McAfee;i="6800,10657,11734"; a="85625258" X-IronPort-AV: E=Sophos;i="6.23,129,1770624000"; d="scan'208";a="85625258" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2026 06:48:14 -0700 X-CSE-ConnectionGUID: e7E65dTnSvqjK5FDSo1dtA== X-CSE-MsgGUID: Zmc4c1UFSVOCLkOjOibJ1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,129,1770624000"; d="scan'208";a="227090097" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.244.180]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2026 06:48:11 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Ankit Nautiyal , Tvrtko Ursulin Subject: [PATCH 6.19.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Date: Thu, 19 Mar 2026 15:47:51 +0200 Message-ID: <20260319134752.1355010-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319134752.1355010-1-jouni.hogander@intel.com> References: <2026031712-strep-autopilot-0999@gregkh> <20260319134752.1355010-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit bb5f1cd10101c2567bff4d0e760b74aee7c42f44 upstream. There are slice row per frame and pic height configuration in DSC Selective Update Parameter Set 1 register. Add helper for configuring these. v2: - Add WARN_ON_ONCE if vdsc instances per pipe > 2 - instead of checking vdsc instances per pipe being > 1 check == 2 Bspec: 71709 Signed-off-by: Jouni Högander Reviewed-by: Ankit Nautiyal Link: https://patch.msgid.link/20260304113011.626542-4-jouni.hogander@intel.com (cherry picked from commit c8698d61aeb3f70fe33761ee9d3d0e131b5bc2eb) Signed-off-by: Tvrtko Ursulin [tursulin: fixup forward declaration conflict] (cherry picked from commit bb5f1cd10101c2567bff4d0e760b74aee7c42f44) --- drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 0e727fc5e80c..b08e677fa2b3 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -767,6 +767,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, sizeof(dp_dsc_pps_sdp)); } +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, int su_lines) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + enum pipe pipe = crtc->pipe; + int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); + int slice_row_per_frame = su_lines / vdsc_cfg->slice_height; + u32 val; + + drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height); + drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2); + + val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame); + val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines); + + intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val); + + if (vdsc_instances_per_pipe == 2) + intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val); +} + static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ? diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 99f64ac54b27..99bb9042592a 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -13,6 +13,7 @@ struct drm_printer; enum transcoder; struct intel_crtc; struct intel_crtc_state; +struct intel_dsb; struct intel_encoder; bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state); @@ -31,6 +32,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, int su_lines); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state); -- 2.43.0