From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20FFA126BF1 for ; Thu, 19 Mar 2026 13:48:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773928102; cv=none; b=oFqzUkjMLMTeNvjo5wgBm/S3JTaFf03tDGlNx5gZ1avXE/6BUM9kVhFstPoS3We3ykn1CqUsS+RkmYqkTH17lfVHClHkHJCmbVPz8IVBeZ3j8mxFWDO9w+Mz8fOJ37Hoo9/IGL6dHT1KLB/xOVQlC223BlYx2WtXBNM7SCU2nRY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773928102; c=relaxed/simple; bh=bWVka/Jbv2jznZM8odidbSPag891v42TlHms2+l61J0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hrjxcg8FiYNCqCr/38X4R3fLOuiLkzBClmX18Ac5GS7DkwlWMj63F5VTUaWwaDOaHS9vHZLt322coCacbL1NUf+mQwXwwYtfAF4f/2FzZPvc6iYy80r29J0Itv3d+pJkmj8LXkhPE0mKtIu99vAA8PqHSlcjai6uOFYOdXO3Xds= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=d1EXtXJF; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="d1EXtXJF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773928100; x=1805464100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bWVka/Jbv2jznZM8odidbSPag891v42TlHms2+l61J0=; b=d1EXtXJFbnWW5niSW04Xp93pgCZxppkXRQ6D2PGA5QoXVnBVWj3Sj6Pp XvzRzN0AxXd53b0emg3EuWtpLKRETiKbEXmM9DEDN5oa72tz4W2XzQpaA YNXbzAUHIuvHSROhycy1hnJnM9ZOurLmzWq1tfiS6SDzbaZdi2zkj+fXS tNE6//ydGnZGNoLE+hQCev7p3rNFbZ3Fq1mTXILahVFdifPkpxG2VS2vB lodmgYA/g0j18yYVK00rMW0kmG2osh8pVQ4xAD1ih4ewUA29L8icHAjse RYL0zAYKKpRoBCQbdCheiRyLyiMPFiocajxUn/1/e+5to4Yk/CTiqH9QX w==; X-CSE-ConnectionGUID: iRQEkgRHSqS8cBFNgWcAXw== X-CSE-MsgGUID: rfJLk/4PQaqvX92NW0GmHA== X-IronPort-AV: E=McAfee;i="6800,10657,11734"; a="85625279" X-IronPort-AV: E=Sophos;i="6.23,129,1770624000"; d="scan'208";a="85625279" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2026 06:48:20 -0700 X-CSE-ConnectionGUID: Wx5pJ/RJSgaLkEDRD0Hw6Q== X-CSE-MsgGUID: Ggxj8GdzT2acFQ3rgTB5ng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,129,1770624000"; d="scan'208";a="227090125" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.244.180]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2026 06:48:17 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Ankit Nautiyal , Tvrtko Ursulin Subject: [PATCH 6.19.y 3/3] drm/i915/psr: Write DSC parameters on Selective Update in ET mode Date: Thu, 19 Mar 2026 15:47:52 +0200 Message-ID: <20260319134752.1355010-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319134752.1355010-1-jouni.hogander@intel.com> References: <2026031712-strep-autopilot-0999@gregkh> <20260319134752.1355010-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 upstream. There are slice row per frame and pic height parameters in DSC that needs to be configured on every Selective Update in Early Transport mode. Use helper provided by DSC code to configure these on Selective Update when in Early Transport mode. Also fill crtc_state->psr2_su_area with full frame area on full frame update for DSC calculation. v2: move psr2_su_area under skip_sel_fetch_set_loop label Bspec: 68927, 71709 Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Cc: # v6.9+ Signed-off-by: Jouni Högander Reviewed-by: Ankit Nautiyal Link: https://patch.msgid.link/20260304113011.626542-5-jouni.hogander@intel.com (cherry picked from commit 3140af2fab505a4cd47d516284529bf1585628be) Signed-off-by: Tvrtko Ursulin (cherry picked from commit 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6) --- drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 44063b578354..5690797403ba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2597,6 +2597,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), crtc_state->pipe_srcsz_early_tpt); + + if (!crtc_state->dsc.compression_enable) + return; + + intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, + drm_rect_height(&crtc_state->psr2_su_area)); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, @@ -2991,6 +2997,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, } skip_sel_fetch_set_loop: + if (full_update) + clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src, + &crtc_state->pipe_src); + psr2_man_trk_ctl_calc(crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt = psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); -- 2.43.0