* FAILED: patch "[PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET" failed to apply to 6.18-stable tree
@ 2026-03-17 13:23 gregkh
2026-03-18 13:24 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
0 siblings, 1 reply; 5+ messages in thread
From: gregkh @ 2026-03-17 13:23 UTC (permalink / raw)
To: jouni.hogander, ankit.k.nautiyal, stable, tursulin; +Cc: stable
The patch below does not apply to the 6.18-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.18.y
git checkout FETCH_HEAD
git cherry-pick -x 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<stable@vger.kernel.org>' --in-reply-to '2026031759-ravine-derived-5582@gregkh' --subject-prefix 'PATCH 6.18.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Wed, 4 Mar 2026 13:30:11 +0200
Subject: [PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET
mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
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There are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
area on full frame update for DSC calculation.
v2: move psr2_su_area under skip_sel_fetch_set_loop label
Bspec: 68927, 71709
Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-5-jouni.hogander@intel.com
(cherry picked from commit 3140af2fab505a4cd47d516284529bf1585628be)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3848cd4fba0e..b7302a32ded4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2619,6 +2619,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
crtc_state->pipe_srcsz_early_tpt);
+
+ if (!crtc_state->dsc.compression_enable)
+ return;
+
+ intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
+ drm_rect_height(&crtc_state->psr2_su_area));
}
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -3040,6 +3046,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
}
skip_sel_fetch_set_loop:
+ if (full_update)
+ clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
+ &crtc_state->pipe_src);
+
psr2_man_trk_ctl_calc(crtc_state, full_update);
crtc_state->pipe_srcsz_early_tpt =
psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions
2026-03-17 13:23 FAILED: patch "[PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET" failed to apply to 6.18-stable tree gregkh
@ 2026-03-18 13:24 ` Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Jouni Högander
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jouni Högander @ 2026-03-18 13:24 UTC (permalink / raw)
To: stable; +Cc: Jouni Högander, Ankit Nautiyal, Tvrtko Ursulin
commit c2c79c6d5b939ae8a42ddb884f576bddae685672 upstream.
Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.
Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
(cherry picked from commit 24f96d903daf3dcf8fafe84d3d22b80ef47ba493)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
(cherry picked from commit c2c79c6d5b939ae8a42ddb884f576bddae685672)
---
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 2d478a84b07c..2b2e3c1b8138 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -196,6 +196,18 @@
#define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
#define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
+#define _LNL_DSC0_SU_PARAMETER_SET_0_PA 0x78064
+#define _LNL_DSC1_SU_PARAMETER_SET_0_PA 0x78164
+#define _LNL_DSC0_SU_PARAMETER_SET_0_PB 0x78264
+#define _LNL_DSC1_SU_PARAMETER_SET_0_PB 0x78364
+#define LNL_DSC0_SU_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB)
+#define LNL_DSC1_SU_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB)
+
+#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK REG_GENMASK(31, 20)
+#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(rows) REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))
+#define DSC_SUPS0_SU_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define DSC_SUPS0_SU_PIC_HEIGHT(h) REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h))
+
/* Icelake Rate Control Buffer Threshold Registers */
#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 6.18.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters
2026-03-18 13:24 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
@ 2026-03-18 13:24 ` Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 3/3] drm/i915/psr: Write DSC parameters on Selective Update in ET mode Jouni Högander
2026-03-19 10:40 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Greg KH
2 siblings, 0 replies; 5+ messages in thread
From: Jouni Högander @ 2026-03-18 13:24 UTC (permalink / raw)
To: stable; +Cc: Jouni Högander, Ankit Nautiyal, Tvrtko Ursulin
commit bb5f1cd10101c2567bff4d0e760b74aee7c42f44 upstream.
There are slice row per frame and pic height configuration in DSC Selective
Update Parameter Set 1 register. Add helper for configuring these.
v2:
- Add WARN_ON_ONCE if vdsc instances per pipe > 2
- instead of checking vdsc instances per pipe being > 1 check == 2
Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-4-jouni.hogander@intel.com
(cherry picked from commit c8698d61aeb3f70fe33761ee9d3d0e131b5bc2eb)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
[tursulin: fixup forward declaration conflict]
(cherry picked from commit bb5f1cd10101c2567bff4d0e760b74aee7c42f44)
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af1..4e701ea0bb23 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -751,6 +751,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
sizeof(dp_dsc_pps_sdp));
}
+void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state, int su_lines)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ enum pipe pipe = crtc->pipe;
+ int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+ int slice_row_per_frame = su_lines / vdsc_cfg->slice_height;
+ u32 val;
+
+ drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
+ drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
+
+ val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
+ val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
+
+ intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
+
+ if (vdsc_instances_per_pipe == 2)
+ intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
+}
+
static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
return is_pipe_dsc(crtc, cpu_transcoder) ?
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 9e2812f99dd7..b77d30b61a32 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -13,6 +13,7 @@ struct drm_printer;
enum transcoder;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_dsb;
struct intel_encoder;
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
@@ -29,6 +30,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state, int su_lines);
void intel_vdsc_state_dump(struct drm_printer *p, int indent,
const struct intel_crtc_state *crtc_state);
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 6.18.y 3/3] drm/i915/psr: Write DSC parameters on Selective Update in ET mode
2026-03-18 13:24 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Jouni Högander
@ 2026-03-18 13:24 ` Jouni Högander
2026-03-19 10:40 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Greg KH
2 siblings, 0 replies; 5+ messages in thread
From: Jouni Högander @ 2026-03-18 13:24 UTC (permalink / raw)
To: stable; +Cc: Jouni Högander, Ankit Nautiyal, Tvrtko Ursulin
commit 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 upstream.
There are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
area on full frame update for DSC calculation.
v2: move psr2_su_area under skip_sel_fetch_set_loop label
Bspec: 68927, 71709
Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-5-jouni.hogander@intel.com
(cherry picked from commit 3140af2fab505a4cd47d516284529bf1585628be)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
(cherry picked from commit 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6)
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 38d1df919d1a..00d490b841cb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -50,6 +50,7 @@
#include "intel_snps_phy.h"
#include "intel_step.h"
#include "intel_vblank.h"
+#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "skl_universal_plane.h"
@@ -2489,6 +2490,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
crtc_state->pipe_srcsz_early_tpt);
+
+ if (!crtc_state->dsc.compression_enable)
+ return;
+
+ intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
+ drm_rect_height(&crtc_state->psr2_su_area));
}
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -2883,6 +2890,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
}
skip_sel_fetch_set_loop:
+ if (full_update)
+ clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
+ &crtc_state->pipe_src);
+
psr2_man_trk_ctl_calc(crtc_state, full_update);
crtc_state->pipe_srcsz_early_tpt =
psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions
2026-03-18 13:24 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 3/3] drm/i915/psr: Write DSC parameters on Selective Update in ET mode Jouni Högander
@ 2026-03-19 10:40 ` Greg KH
2 siblings, 0 replies; 5+ messages in thread
From: Greg KH @ 2026-03-19 10:40 UTC (permalink / raw)
To: Jouni Högander; +Cc: stable, Ankit Nautiyal, Tvrtko Ursulin
On Wed, Mar 18, 2026 at 03:24:10PM +0200, Jouni Högander wrote:
> commit c2c79c6d5b939ae8a42ddb884f576bddae685672 upstream.
>
> Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
> DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
> Transport configuration.
>
> Bspec: 71709
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
> (cherry picked from commit 24f96d903daf3dcf8fafe84d3d22b80ef47ba493)
> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
> (cherry picked from commit c2c79c6d5b939ae8a42ddb884f576bddae685672)
> ---
> drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
We need a 6.19.y version of this before we can take older versions :(
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-03-19 10:40 UTC | newest]
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2026-03-17 13:23 FAILED: patch "[PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET" failed to apply to 6.18-stable tree gregkh
2026-03-18 13:24 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 2/3] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Jouni Högander
2026-03-18 13:24 ` [PATCH 6.18.y 3/3] drm/i915/psr: Write DSC parameters on Selective Update in ET mode Jouni Högander
2026-03-19 10:40 ` [PATCH 6.18.y 1/3] drm/i915/dsc: Add Selective Update register definitions Greg KH
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