From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 666713AB269; Mon, 23 Mar 2026 14:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277011; cv=none; b=LYluGNgpP65dHBGg9ULb8rIQPLmhQ06J3baJ5aVh8DHGgj7owPzZiMNaCv8cT8HwIywzZhszPtofETqU9RcwIxrQc3o+dWEBnQU9jvBbliRvPD4SAwaq34lWHTnr3yYfSWSt5JSZ3pU+A7yZ6MjqbkazaFh940zvLLRr9PfGPSc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277011; c=relaxed/simple; bh=w/XLHwr67dLgZH8L7FtAZAF7R4+4oerYDoCGWBHbm8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Syp2reMRXfh3UHHd+qSYE9yJcZ2vmTOpuZxTE3g/f8uzhPiYpZdSy/G5UqGLGmBaSFi82klmwEY44bMDVohQE/izlRr7HtVktFEVFy5T1eYyQ6WKmHSOQD4cl+UeHMHu6KyJjcCv+LREZ5iJwFi4xgiFLFuSCywbMDp1JaG6bns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Yd8YfqJK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Yd8YfqJK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 013D0C4CEF7; Mon, 23 Mar 2026 14:43:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1774277011; bh=w/XLHwr67dLgZH8L7FtAZAF7R4+4oerYDoCGWBHbm8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yd8YfqJKZp7NLUvtVoxxwY3ww9mBVRljW0QHcdDIsaKLF6wq9bd/IfQgNR9qkjPx9 z80eLrqgI8uCuELxeJptZYQvgzlYbO8zsA6i3SN4DYDccacPyOQrW9gIZYBP6MR9V6 2BsZ4wQnelJsOPsDjKeqnNm2CsOQHtpdtHyhNx+k= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, "Naveen N Rao (AMD)" , Sean Christopherson , Sasha Levin Subject: [PATCH 6.12 244/460] KVM: SVM: Limit AVIC physical max index based on configured max_vcpu_ids Date: Mon, 23 Mar 2026 14:44:00 +0100 Message-ID: <20260323134532.496214172@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260323134526.647552166@linuxfoundation.org> References: <20260323134526.647552166@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Naveen N Rao [ Upstream commit 574ef752d4aea04134bc121294d717f4422c2755 ] KVM allows VMMs to specify the maximum possible APIC ID for a virtual machine through KVM_CAP_MAX_VCPU_ID capability so as to limit data structures related to APIC/x2APIC. Utilize the same to set the AVIC physical max index in the VMCB, similar to VMX. This helps hardware limit the number of entries to be scanned in the physical APIC ID table speeding up IPI broadcasts for virtual machines with smaller number of vCPUs. Unlike VMX, SVM AVIC requires a single page to be allocated for the Physical APIC ID table and the Logical APIC ID table, so retain the existing approach of allocating those during VM init. Signed-off-by: Naveen N Rao (AMD) Link: https://lore.kernel.org/r/adb07ccdb3394cd79cb372ba6bcc69a4e4d4ef54.1757009416.git.naveen@kernel.org Signed-off-by: Sean Christopherson Stable-dep-of: 87d0f901a9bd ("KVM: SVM: Set/clear CR8 write interception when AVIC is (de)activated") Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/svm/avic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -85,6 +85,7 @@ struct amd_svm_iommu_ir { static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb = svm->vmcb01.ptr; + struct kvm *kvm = svm->vcpu.kvm; vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; @@ -100,7 +101,8 @@ static void avic_activate_vmcb(struct vc */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |= X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |= X2AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= min(kvm->arch.max_vcpu_ids - 1, + X2AVIC_MAX_PHYSICAL_ID); /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -111,7 +113,8 @@ static void avic_activate_vmcb(struct vc kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= min(kvm->arch.max_vcpu_ids - 1, + AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); }