From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC75B26ED46; Mon, 23 Mar 2026 14:59:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277999; cv=none; b=ExtJB6+ivOv6vdyuP5V30XKHevkxpvGuYTN5DYNR2CFdr83a4+Ae8UiTuDjDANhwcyHteo8B894UtNe2wOa5guNjMRkvmYMarsUv2AQasfnUvGg7M72nYyjXssjj+4ocElytydbQwLUCP8CJ+OQnalxSDBX3fW5+6cFNWi3E64o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277999; c=relaxed/simple; bh=Pb3n0EmLggoQG+eFLHXFxMUV0FYJBtmt/sM8o9bQWMo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DTGhZ24H40Bgwi9IoQGYzSlMq2/N9YXjqqOZtXYxdOR3pjuD7INYLAdENhdLEJjL5KID8MV6/NyBrJ/UQ6ioZRmpUS06DpaGtR2rbbo//ahAOQM2PtPFheicSELJAxjaCDOT8Acd1c4RAGKhcY6Qxx24AyQUaAM3g7ihBaIFUWo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=TWAOtS3s; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="TWAOtS3s" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 490B0C4CEF7; Mon, 23 Mar 2026 14:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1774277999; bh=Pb3n0EmLggoQG+eFLHXFxMUV0FYJBtmt/sM8o9bQWMo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TWAOtS3sdiwtC42VNfMwoYn/prUK6KBSGDlo9wJlJUIhQoeb0JztpQjqkTt7dlDkb jesQxeK/TtfrJ0Cu7i9d3ych1fh6y9os9RowGTR7uQw+ghfxJgR/4uEDxmTE3gVKE/ +QSbfaA4JYm3Ry5Hpf3o+DkiY/6eVRhGwrSCaxV8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Guruvendra Punugupati , Raju Rangoju , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.6 142/567] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds Date: Mon, 23 Mar 2026 14:41:02 +0100 Message-ID: <20260323134537.329670164@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260323134533.749096647@linuxfoundation.org> References: <20260323134533.749096647@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Raju Rangoju [ Upstream commit 9439a661c2e80485406ce2c90b107ca17858382d ] Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits to 3 bits to properly support all speed settings. The MAC_TCR register's SS field encoding requires 3 bits to represent all supported speeds: - 0x00: 10Gbps (XGMII) - 0x02: 2.5Gbps (GMII) / 100Mbps - 0x03: 1Gbps / 10Mbps - 0x06: 2.5Gbps (XGMII) - P100a only With only 2 bits, values 0x04-0x07 cannot be represented, which breaks 2.5G XGMII mode on newer platforms and causes incorrect speed select values to be programmed. Fixes: 07445f3c7ca1 ("amd-xgbe: Add support for 10 Mbps speed") Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Raju Rangoju Link: https://patch.msgid.link/20260226170753.250312-1-Raju.Rangoju@amd.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/amd/xgbe/xgbe-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h index aa25a8a0a106f..d99d2295eab0f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h @@ -514,7 +514,7 @@ #define MAC_SSIR_SSINC_INDEX 16 #define MAC_SSIR_SSINC_WIDTH 8 #define MAC_TCR_SS_INDEX 29 -#define MAC_TCR_SS_WIDTH 2 +#define MAC_TCR_SS_WIDTH 3 #define MAC_TCR_TE_INDEX 0 #define MAC_TCR_TE_WIDTH 1 #define MAC_TCR_VNE_INDEX 24 -- 2.51.0