From: Rosen Penev <rosenp@gmail.com>
To: stable@vger.kernel.org
Cc: "Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Pan, Xinhui" <Xinhui.Pan@amd.com>,
"David Airlie" <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Bin Lan" <bin.lan.cn@windriver.com>,
"He Zhe" <zhe.he@windriver.com>,
"Vitaly Prosyak" <vitaly.prosyak@amd.com>,
"Alex Hung" <alex.hung@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Timur Kristóf" <timur.kristof@gmail.com>,
"Mario Limonciello" <Mario.Limonciello@amd.com>,
"Ray Wu" <ray.wu@amd.com>, "Wayne Lin" <wayne.lin@amd.com>,
"Roman Li" <Roman.Li@amd.com>, "Eric Yang" <Eric.Yang2@amd.com>,
"Tony Cheng" <Tony.Cheng@amd.com>,
"Mauro Rossi" <issor.oruam@gmail.com>,
amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM
DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH for 6.12 4/9] drm/amd/display: Reject modes with too high pixel clock on DCE6-10
Date: Thu, 26 Mar 2026 16:47:11 -0700 [thread overview]
Message-ID: <20260326234716.16723-5-rosenp@gmail.com> (raw)
In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com>
From: Timur Kristóf <timur.kristof@gmail.com>
[ Upstream commit 118800b0797a046adaa2a8e9dee9b971b78802a7 ]
Reject modes with a pixel clock higher than the maximum display
clock. Use 400 MHz as a fallback value when the maximum display
clock is not known. Pixel clocks that are higher than the display
clock just won't work and are not supported.
With the addition of the YUV422 fallback, DC can now accidentally
select a mode requiring higher pixel clock than actually supported
when the DP version supports the required bandwidth but the clock
is otherwise too high for the display engine. DCE 6-10 don't
support these modes but they don't have a bandwidth calculation
to reject them properly.
Fixes: db291ed1732e ("drm/amd/display: Add fallback path for YCBCR422")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
.../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +++
.../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 +++++
drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 10 +++++++++-
.../amd/display/dc/resource/dce100/dce100_resource.c | 10 +++++++++-
.../drm/amd/display/dc/resource/dce80/dce80_resource.c | 10 +++++++++-
5 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index b268c367c27c..a2e100aa3cba 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -460,6 +460,9 @@ void dce_clk_mgr_construct(
clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
+ base->clks.max_supported_dispclk_khz =
+ clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+
dce_clock_read_integrated_info(clk_mgr);
dce_clock_read_ss_info(clk_mgr);
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
index a39641a0ff09..69dd80d9f738 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -147,6 +147,8 @@ void dce60_clk_mgr_construct(
struct dc_context *ctx,
struct clk_mgr_internal *clk_mgr)
{
+ struct clk_mgr *base = &clk_mgr->base;
+
dce_clk_mgr_construct(ctx, clk_mgr);
memcpy(clk_mgr->max_clks_by_state,
@@ -157,5 +159,8 @@ void dce60_clk_mgr_construct(
clk_mgr->clk_mgr_shift = &disp_clk_shift;
clk_mgr->clk_mgr_mask = &disp_clk_mask;
clk_mgr->base.funcs = &dce60_funcs;
+
+ base->clks.max_supported_dispclk_khz =
+ clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
index 8db9f7514466..7886a2a55caf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -34,6 +34,7 @@
#include "stream_encoder.h"
#include "resource.h"
+#include "clk_mgr.h"
#include "include/irq_service_interface.h"
#include "irq/dce60/irq_service_dce60.h"
#include "dce110/dce110_timing_generator.h"
@@ -870,10 +871,17 @@ static bool dce60_validate_bandwidth(
{
int i;
bool at_least_one_pipe = false;
+ struct dc_stream_state *stream = NULL;
+ const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (context->res_ctx.pipe_ctx[i].stream)
+ stream = context->res_ctx.pipe_ctx[i].stream;
+ if (stream) {
at_least_one_pipe = true;
+
+ if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
}
if (at_least_one_pipe) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index 53a5f4cb648c..6717ed84a032 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -29,6 +29,7 @@
#include "stream_encoder.h"
#include "resource.h"
+#include "clk_mgr.h"
#include "include/irq_service_interface.h"
#include "virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
@@ -843,10 +844,17 @@ static bool dce100_validate_bandwidth(
{
int i;
bool at_least_one_pipe = false;
+ struct dc_stream_state *stream = NULL;
+ const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (context->res_ctx.pipe_ctx[i].stream)
+ stream = context->res_ctx.pipe_ctx[i].stream;
+ if (stream) {
at_least_one_pipe = true;
+
+ if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
}
if (at_least_one_pipe) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index a73d3c6ef425..af4a45718c7c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -32,6 +32,7 @@
#include "stream_encoder.h"
#include "resource.h"
+#include "clk_mgr.h"
#include "include/irq_service_interface.h"
#include "irq/dce80/irq_service_dce80.h"
#include "dce110/dce110_timing_generator.h"
@@ -876,10 +877,17 @@ static bool dce80_validate_bandwidth(
{
int i;
bool at_least_one_pipe = false;
+ struct dc_stream_state *stream = NULL;
+ const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (context->res_ctx.pipe_ctx[i].stream)
+ stream = context->res_ctx.pipe_ctx[i].stream;
+ if (stream) {
at_least_one_pipe = true;
+
+ if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
}
if (at_least_one_pipe) {
--
2.53.0
next prev parent reply other threads:[~2026-03-26 23:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 23:47 [PATCH for 6.12 0/9] drm: amdgpu: backport suspend fixes for Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 1/9] drm/amd/amdgpu: decouple ASPM with pcie dpm Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 2/9] drm/amd/amdgpu: disable ASPM in some situations Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 3/9] drm/amd/display: Disable fastboot on DCE 6 too Rosen Penev
2026-03-26 23:47 ` Rosen Penev [this message]
2026-03-26 23:47 ` [PATCH for 6.12 5/9] drm/amd/display: Keep PLL0 running on DCE 6.0 and 6.4 Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 6/9] drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 7/9] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15% Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 8/9] drm/amd/display: Disable scaling on DCE6 for now Rosen Penev
2026-03-26 23:47 ` [PATCH for 6.12 9/9] drm/amd: Disable ASPM on SI Rosen Penev
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