From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F6312D63E8; Tue, 31 Mar 2026 17:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774976711; cv=none; b=cUvyZnc3K05omvkm1ZJJ2j4BNC/BVaGSJRFXIdAkhNYm8YnM3VTkWQtZoRfrBLhCjQJWztNtX1PP9VwDQPpXry3enECq6Ip1MDPb38+3kuedjp9+ZRNE9VIU03X3OTx5Z5jhSA+q3iR0MbZchlHQIXmvAbZunXYAJ3WOZH1wu64= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774976711; c=relaxed/simple; bh=NdC6bJoR7rub44bn5+05l20GmdXoyUCmTamqoqOqw0s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WzGYFFwt1k+YQR9d4zuhjIr31qITJnlAfGT9oyuIwV2Cd87cxnzQCLApPpV1g99E/E+Or/tJ4YJPNXCL6uXyxHwQHvu+TM4x2LxmzqtLpYYiXhhwx1uww1mngU6mveIy2bCNLdj4KehgAp1orSqWeZOtaJ7lWQyGxJCE2DgMf18= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=ci/2B1Le; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="ci/2B1Le" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 174D7C19423; Tue, 31 Mar 2026 17:05:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1774976711; bh=NdC6bJoR7rub44bn5+05l20GmdXoyUCmTamqoqOqw0s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ci/2B1Le8DXVJwUD2gODBf1eQ18uH555IssPvzM/LoqS30LrC4KghVClyBDzFzMLu AuttX+RD05O7ZOFgOWF3cgh3rRWQzB0szOiJdldl1uzv6Sl1bOuXasO/eobVMYJOsa BZnieL3zUJ4TwBKjC1osOtTnp8BfsoH4hDIKV/oc= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Srinivas Pandruvada , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 6.18 197/309] platform/x86: ISST: Correct locked bit width Date: Tue, 31 Mar 2026 18:21:40 +0200 Message-ID: <20260331161800.707517074@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260331161753.468533260@linuxfoundation.org> References: <20260331161753.468533260@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Srinivas Pandruvada commit fbddf68d7b4e1e6da7a78dd7fbd8ec376536584a upstream. SST-PP locked bit width is set to three bits. It should be only one bit. Use SST_PP_LOCK_WIDTH define instead of SST_PP_LEVEL_WIDTH. Fixes: ea009e4769fa ("platform/x86: ISST: Add SST-PP support via TPMI") Signed-off-by: Srinivas Pandruvada Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260323153635.3263828-1-srinivas.pandruvada@linux.intel.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c @@ -871,7 +871,7 @@ static int isst_if_get_perf_level(void _ _read_pp_info("current_level", perf_level.current_level, SST_PP_STATUS_OFFSET, SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE) _read_pp_info("locked", perf_level.locked, SST_PP_STATUS_OFFSET, - SST_PP_LOCK_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE) + SST_PP_LOCK_START, SST_PP_LOCK_WIDTH, SST_MUL_FACTOR_NONE) _read_pp_info("feature_state", perf_level.feature_state, SST_PP_STATUS_OFFSET, SST_PP_FEATURE_STATE_START, SST_PP_FEATURE_STATE_WIDTH, SST_MUL_FACTOR_NONE) perf_level.enabled = !!(power_domain_info->sst_header.cap_mask & BIT(1));