From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CE7D44B680 for ; Wed, 1 Apr 2026 16:17:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775060222; cv=none; b=FS6H/+eah/r1cEHWG8cj4hyE26tz6UMeHIovP/7yT0W99Bpnv+bGRCkShKYf3N7YkXdvOBvlP35/iXAaIKtWuCNtJdb+bLjFWfNbxESrbI0UdLycKjQY1YCxrTAJBFxlcwe9QFHPHdCvPbuOl5lnvBr2qXbFtjfnK1eCKmMna1I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775060222; c=relaxed/simple; bh=jah76msZHSvgCQuq79xNP4DvNR/lFduJZIHhtaC4+hk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t9sYi2/LyYvmM01r4ZIH3m6Sxs2mOiAl56Lu/1LSRd8dAEUFXLoiPbowGuD4endE4euoaXlX4LRxtpxbfcVfeZSu62Ae7Ym9PnBke6fBIjj6qe8/EnnmdhDALgF2IfWUaXkgE5H8z6iWbkw5XirBT2T5OMMso9rzF3tbBk9oN34= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kXJMw4wW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kXJMw4wW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4517C2BCB2; Wed, 1 Apr 2026 16:17:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775060221; bh=jah76msZHSvgCQuq79xNP4DvNR/lFduJZIHhtaC4+hk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kXJMw4wWBDSQQq6T5JzcfRl/36y6nPwhYBYrTvDYofccV8LzTkndhH4UI/9/nSe/q B8aTkFleiLld1idxIAfaaUCtvEN2wjYTtN5AQ64rezUL701H2I8LyLyNhAlaO/9K9T OqdL+F1P9pg+7nMl5atUM6PpJlNv9XuTlxO2TQEGu1F8GfABGDbwVq6UrQU+8Klnrh VVYvXX591KINjiI0ivS0Bo1z7R8/bG1YtJ78iXYE5aIYbx/0p3LL8XaZLOh8VaiSOn pignkePVkF3Wt/jzlAeJlPatWD8EiqQ/ZBkWl8mjXXEGhTUaAbz/JQYtPc6ojiS+q7 U4dyh0S2ehFlQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Claudiu Beznea , Biju Das , Frank Li , Claudiu Beznea , Vinod Koul , Sasha Levin Subject: [PATCH 5.15.y] dmaengine: sh: rz-dmac: Move CHCTRL updates under spinlock Date: Wed, 1 Apr 2026 12:16:58 -0400 Message-ID: <20260401161658.115456-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026033044-applause-erased-d411@gregkh> References: <2026033044-applause-erased-d411@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea [ Upstream commit 89a8567d84bde88cb7cdbbac2ab2299c4f991490 ] Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL register. To avoid concurrency issues when configuring functionalities exposed by this registers, take the virtual channel lock. All other CHCTRL updates were already protected by the same lock. Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers but this does not ensure race-free access. Remove the local IRQ disable/enable code as well. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Reviewed-by: Biju Das Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20260316133252.240348-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul [ replaced scoped_guard(spinlock_irqsave, ...) ] Signed-off-by: Sasha Levin --- drivers/dma/sh/rz-dmac.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index e6f8257c76672..acab58b02dbe9 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -283,13 +283,10 @@ static void rz_dmac_disable_hw(struct rz_dmac_chan *channel) { struct dma_chan *chan = &channel->vc.chan; struct rz_dmac *dmac = to_rz_dmac(chan->device); - unsigned long flags; dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); - local_irq_save(flags); rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); - local_irq_restore(flags); } static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars) @@ -536,8 +533,8 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) unsigned int i; LIST_HEAD(head); - rz_dmac_disable_hw(channel); spin_lock_irqsave(&channel->vc.lock, flags); + rz_dmac_disable_hw(channel); for (i = 0; i < DMAC_NR_LMDESC; i++) lmdesc[i].header = 0; @@ -646,13 +643,17 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel) { struct dma_chan *chan = &channel->vc.chan; struct rz_dmac *dmac = to_rz_dmac(chan->device); + unsigned long flags; u32 chstat, chctrl; chstat = rz_dmac_ch_readl(channel, CHSTAT, 1); if (chstat & CHSTAT_ER) { dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n", channel->index, chstat); + + spin_lock_irqsave(&channel->vc.lock, flags); rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + spin_unlock_irqrestore(&channel->vc.lock, flags); goto done; } -- 2.53.0