From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EE762FFFA4 for ; Mon, 13 Apr 2026 16:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776097594; cv=none; b=Qu+uW2AxLF0scKObyIzxdyn4gUSLt+g2Fq1jGb7hc7OZq7PNsl6qjOlNrmkK/rrcoBdR+naIsDw2AEB+358u0G48MaO0die05gwG58kdcTA8pENDmsqhM/uUL4McgSS4FyQWv9IIb8GC5Hq5mPjsQ0kyTYLcPmNJ0eOe5z17Ex8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776097594; c=relaxed/simple; bh=qHOE7XqUw2SSH0eGQ/Xlzi9TXNBWltl6yqEe6zx6PaU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aTZjJyMXzCtXmHrd6PK64//p5+PWUlV355AvFrepD27SFuKle1VBpl1JTGT164+8kDeWROzx5p7qlk8TlQWAPGQEracN5J+xfcjPmyT/llfFNqAi10xAck6OM8NMmwRMIN8npBdQQ7MCnOG02V/Mv9ZYKuAHSBE5M0z9faH5hlM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CzGFkreA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CzGFkreA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 903FDC2BCAF; Mon, 13 Apr 2026 16:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776097594; bh=qHOE7XqUw2SSH0eGQ/Xlzi9TXNBWltl6yqEe6zx6PaU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CzGFkreA2DXS/89kovH4RGKFMemDNBb9AgmgeDm4OdC1VaI6KoPHo9KMIsAy+GKZp a6FXkORvOiJ0DugHty1MeYPl+kTxkcUKmiTuRx9F6nG17g6D+vfIC9so7GoA9oPo3c ZOqJ71hUzdhFV57Upd35M4fysBPOB+1Fmkup0dc+e8Lp/HkNKZgxDWA213i3jADRCG Pinn7lO2n3WjJlvOmG2+S3AWKRZ5pOKlGrIg6KuhUn6YoSE2XKna7YjyNjudr9Fwgy 2YIys9lWjl1DU3k3b61XDldjKmyEdTkkv4WI5/VMe1Oga/Ctv2QhTBY5NQthMf+9AE b7Fn5xIBQC1/w== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Mika Kahola , Joonas Lahtinen , Sasha Levin Subject: [PATCH 6.6.y] drm/i915/psr: Do not use pipe_src as borders for SU area Date: Mon, 13 Apr 2026 12:26:31 -0400 Message-ID: <20260413162631.3289330-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026041313-ricotta-reattach-82b9@gregkh> References: <2026041313-ricotta-reattach-82b9@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Jouni Högander [ Upstream commit 75519f5df2a9b23f7bf305e12dc9a6e3e65c24b7 ] This far using crtc_state->pipe_src as borders for Selective Update area haven't caused visible problems as drm_rect_width(crtc_state->pipe_src) == crtc_state->hw.adjusted_mode.crtc_hdisplay and drm_rect_height(crtc_state->pipe_src) == crtc_state->hw.adjusted_mode.crtc_vdisplay when pipe scaling is not used. On the other hand using pipe scaling is forcing full frame updates and all the Selective Update area calculations are skipped. Now this improper usage of crtc_state->pipe_src is causing following warnings: <4> [7771.978166] xe 0000:00:02.0: [drm] drm_WARN_ON_ONCE(su_lines % vdsc_cfg->slice_height) after WARN_ON_ONCE was added by commit: "drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters" These warnings are seen when DSC and pipe scaling are enabled simultaneously. This is because on full frame update SU area is improperly set as pipe_src which is not aligned with DSC slice height. Fix these by creating local rectangle using crtc_state->hw.adjusted_mode.crtc_hdisplay and crtc_state->hw.adjusted_mode.crtc_vdisplay. Use this local rectangle as borders for SU area. Fixes: d6774b8c3c58 ("drm/i915: Ensure damage clip area is within pipe area") Cc: # v6.0+ Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola Link: https://patch.msgid.link/20260327114553.195285-1-jouni.hogander@intel.com (cherry picked from commit da0cdc1c329dd2ff09c41fbbe9fbd9c92c5d2c6e) Signed-off-by: Joonas Lahtinen [ omitted hunks for DSC selective update ET alignment infrastructure ] Signed-off-by: Sasha Levin --- drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 5cf3db7058b98..b0818dc8480ed 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1924,9 +1924,9 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, static void clip_area_update(struct drm_rect *overlap_damage_area, struct drm_rect *damage_area, - struct drm_rect *pipe_src) + struct drm_rect *display_area) { - if (!drm_rect_intersect(damage_area, pipe_src)) + if (!drm_rect_intersect(damage_area, display_area)) return; if (overlap_damage_area->y1 == -1) { @@ -2004,6 +2004,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; struct intel_plane_state *new_plane_state, *old_plane_state; struct intel_plane *plane; + struct drm_rect display_area = { + .x1 = 0, + .y1 = 0, + .x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay, + .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, + }; bool full_update = false; int i, ret; @@ -2050,14 +2056,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, damaged_area.y1 = old_plane_state->uapi.dst.y1; damaged_area.y2 = old_plane_state->uapi.dst.y2; clip_area_update(&pipe_clip, &damaged_area, - &crtc_state->pipe_src); + &display_area); } if (new_plane_state->uapi.visible) { damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; clip_area_update(&pipe_clip, &damaged_area, - &crtc_state->pipe_src); + &display_area); } continue; } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { @@ -2065,7 +2071,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; clip_area_update(&pipe_clip, &damaged_area, - &crtc_state->pipe_src); + &display_area); continue; } @@ -2081,7 +2087,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; - clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); + clip_area_update(&pipe_clip, &damaged_area, &display_area); } /* -- 2.53.0