From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 655E030AD00 for ; Wed, 15 Apr 2026 06:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776233998; cv=none; b=G2FqQDzygySjigwm4GXxpjhUsOGWSwh3aq2Zw3TYi4I/pShyQwUqr/TSiut44eOjICADhGCoNKC+L+OTpSahoXFIj5VxdaWp3i41uVxxQJJi8KAJf6x7dP2w8M3MfI4h3yttCM7Tza/ilBV+pu/kxsxIm8IxGHuN9emCNFhoC28= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776233998; c=relaxed/simple; bh=KE9XrWo/Ktyem7WhjCcbZaH6W1xGScXC6A1U7Gz6c9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fJ9qrRcdM3syoPLM9Yr+KjhR610Dib6j5lzJmveg1/1ElFjExLrGFJMl8vLaaMVK7D0BEbM85oU1anRtzHITF043vNVpvTZiQTCmDFTUq1OtaJL8pt2Di6Vekdg1LC7SZX0NlbRYA9nh0xhkyRwwAPb3Rg1yN2GvL7UaagDZnJc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VlH2lxs0; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VlH2lxs0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776233998; x=1807769998; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KE9XrWo/Ktyem7WhjCcbZaH6W1xGScXC6A1U7Gz6c9A=; b=VlH2lxs0n0Ns2+GmOmAz+zOQXcFgb7kqEg5SS5eLofpQRDUJRbK/1wak zm08IYp3KUaY4lpG072z6b2H/77SzcipjKzTWal/PltrLi0AvNavA6RE0 TUdmdDfKKwillkYJRqfmo8zzz5PbcHS17XCh0rXjx9nduSxmVSzHPntZ+ Zhx0caNagEl1kXzC71lsBv68D5ZKcZlxrhFMmdxbO6MziIS3A6Dn6RD5a rVT0rH+TvSy54yTm70oGVfFRoEsfIjp3R3LGvkkAtsLVSXSN15l3gW5tm ie1aZbtvkgRAWRI0tAlWN42QAAJ+lPbWYXXdvqZwb78eu2GZrllJojfpl A==; X-CSE-ConnectionGUID: dxJRECtqSj2p+ne9XF3j1A== X-CSE-MsgGUID: RzX1+tqlRUyFK8NyYYp8+w== X-IronPort-AV: E=McAfee;i="6800,10657,11759"; a="77080172" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="77080172" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 23:19:57 -0700 X-CSE-ConnectionGUID: evCSqyyJR+aKacHwKh4Kxw== X-CSE-MsgGUID: 4bRuZ37ORJKvTXfOXkw3cA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="227675225" Received: from dut6094bmgfrd.fm.intel.com ([10.80.55.31]) by fmviesa008.fm.intel.com with ESMTP; 14 Apr 2026 23:19:57 -0700 From: Jia Yao To: intel-xe@lists.freedesktop.org Cc: Jia Yao , stable@vger.kernel.org, Shuicheng Lin , Mathew Alwin , Michal Mrozek , Matthew Brost , Matthew Auld Subject: [PATCH v8 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Date: Wed, 15 Apr 2026 06:19:51 +0000 Message-ID: <20260415061951.427699-3-jia.yao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415061951.427699-1-jia.yao@intel.com> References: <20260129000147.339361-1-jia.yao@intel.com> <20260415061951.427699-1-jia.yao@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add validation in xe_vm_bind_ioctl() to reject PAT indices with XE_COH_NONE coherency mode when used with DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR. CPU address mirror mappings use system memory that is CPU cached, which makes them incompatible with COH_NONE PAT indices. Allowing COH_NONE with CPU cached buffers is a security risk, as the GPU may bypass CPU caches and read stale sensitive data from DRAM. Although CPU_ADDR_MIRROR does not create an immediate mapping, the backing system memory is still CPU cached. Apply the same PAT coherency restrictions as DRM_XE_VM_BIND_OP_MAP_USERPTR. v2: - Correct fix tag v6: - No change v7: - Correct fix tag v8: - Rebase Fixes: b43e864af0d4 ("drm/xe/uapi: Add DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR") Cc: stable@vger.kernel.org # v6.18 Cc: Shuicheng Lin Cc: Mathew Alwin Cc: Michal Mrozek Cc: Matthew Brost Cc: Matthew Auld Signed-off-by: Jia Yao Reviewed-by: Matthew Auld --- drivers/gpu/drm/xe/xe_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 2408b547ca3d..619a22fa9abe 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3657,7 +3657,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, XE_IOCTL_DBG(xe, obj && op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE && - op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || + (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || is_cpu_addr_mirror)) || XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) && (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || is_cpu_addr_mirror) && -- 2.43.0