Re: [PATCH] drm/xe/xelp: Fix Wa_18022495364

Matt Roper
2026-04-21T17:31:07Z

On Tue, Apr 21, 2026 at 04:09:25PM +0100, Tvrtko Ursulin wrote:
>
> On 20/04/2026 21:29, Matt Roper wrote:
> > On Mon, Apr 20, 2026 at 02:24:05PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 20/04/2026 14:16, Tvrtko Ursulin wrote:
> > > > Command parser relative MMIO addressing needs to be enabled when writing
> > > > to the register.
> > > >
> > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> > > > Fixes: ca33cd271ef9 ("drm/xe/xelp: Add Wa_18022495364")
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > > Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Cc: <stable@vger.kernel.org> # v6.18+
> >
> > I don't think we want/need the stable Cc here; this workaround doesn't
> > apply to any of the Xe2 and later platforms that the Xe driver supports
> > for users. While it's possible for developers to manually override the
> > driver's detection flags and force it to load on Xe1-era platforms that
> > this workaround does apply to, doing so will taint the kernel and we
> > already know that a lot of Xe1 era workarounds aren't implemented.
>
> You are right, I just blindly copied the output of dim fixes. But it doesn't
> matter hugely either way since as long as there is Fixes: it would get
> picked up for -stable anyway.
>
> >
> > > > ---
> > > > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> > > > index 9d12a0d2f0b5..c725cde4508d 100644
> > > > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > > > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > > > @@ -1214,7 +1214,7 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
> > > > if (xe_gt_WARN_ON(lrc->gt, max_len < 3))
> > > > return -ENOSPC;
> > > > - *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);
> > > > + *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_LRM_CS_MMIO | MI_LRI_NUM_REGS(1);
> > >
> > > Or if this register exists only for RCS would it be better to define
> > > CS_DEBUG_MODE2 as the absolute 0x20d8 (as in i915)? Unfortunately the public
> > > TGL PRM does not list neither the register or the workaround so I am not
> > > sure.
> >
> > CS_DEBUG_MODE2 exists on both the RCS and CCS engines, so I think the
> > current register definition is fine.
> >
> > Personally I might have changed the line farther down to
> > CS_DEBUG_MODE2(hwe->mmio_base) so that we're using an absolute offset
> > instead of relative, but adding the MI_LRI_LRM_CS_MMIO flag and passing
> > the relative offset should work fine too.
>
> Good to know, thanks! I am happy to change to absolute if you prefer.
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> Thank you!
>
> I assume someone will pull the patch in?

Yeah, I just pushed it; the CI results weren't available when I checked
yesterday (likely due to the weekend CI farm downtime creating a big
testing backlog).

Thanks.

Matt

>
> Regards,
>
> Tvrtko
>
>

--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation