From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9FA6285072 for ; Fri, 1 May 2026 13:19:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777641540; cv=none; b=sos+8DorwUcTJAMq+sS0imnTwDUkfyArg22F/tkQGYJ9fY9ch0eLZh2nIa9cGo8fWPF8mOAuDXnuq9Ef6vzL4K9JALHosleqddMObs1/yq2hNqElyOV5skMoedusRZ57meGdVxCGS6y9SlB4FuOlbcCRexOAzpomrrfA2PckteM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777641540; c=relaxed/simple; bh=p47eQOiLjEYJnkJpsjgabXWThQjkxRbY63B9AUUNHuA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GWoi2bEr36zzwbHLWpUpmeTFtnTvtF6cWNuv2ev0cZ/VhnEVcZpw5/kLZGRCKpq1vmLEKU4GmCjPMfMxFEdZ4MS+vpZM6sXQhI9G7t0jMLGy9Thcf92juBRkklJBtQSYE0bIr33wQrb17EMDMCZrqdI2pbx5h5byRvZM81Ovdpc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LozZSXGs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LozZSXGs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC083C2BCB4; Fri, 1 May 2026 13:18:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777641540; bh=p47eQOiLjEYJnkJpsjgabXWThQjkxRbY63B9AUUNHuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LozZSXGsDqpu0A4xuJ0hE5dqWdHPdtAmQkd/XWaHSLPpoVI5K9FjQfmYbDP/sE17A 7oXmGKJfC1QQLTSbWFBkvmTKsQi1e+Ns63R0RUa0visu32MiTz2WzB+O8SxcVlTujk O8sjjUGWobfsPVvBOeZXxeJ3ymP+5mACf1dCKbmhBgzrRDIUbWqwVkAaZ/+XC+dcrl wccEM801xmr80F/FyYJuPpqM7J1byTD+0Fy28qV5wG7+ybARMPy5Uo2ygj8c4CO/pZ BI4nKByaXQwFHkzIEhQiD0d6p8xKzkxLOJg61oAiYCGK5x7ULeI2exWVME/CErlwdN frJ7NZom/09/Q== From: Sasha Levin To: stable@vger.kernel.org Cc: Ronak Raheja , Wesley Cheng , Dmitry Baryshkov , Neil Armstrong , Vinod Koul , Sasha Levin Subject: [PATCH 6.18.y 1/2] phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE Date: Fri, 1 May 2026 09:18:55 -0400 Message-ID: <20260501131857.3242270-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026050131-exfoliate-garter-519b@gregkh> References: <2026050131-exfoliate-garter-519b@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Ronak Raheja [ Upstream commit 7044ed6749c8a7d49e67b2f07f42da2f29d26be6 ] Certain platforms may not have the PHY_ENABLE bit set on power on reset. Update the current sequence to explicitly write to enable the PHY_ENABLE bit. This ensures that regardless of the platform, the PHY is properly enabled. Signed-off-by: Ronak Raheja Signed-off-by: Wesley Cheng Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20250920032158.242725-1-wesley.cheng@oss.qualcomm.com Signed-off-by: Vinod Koul Stable-dep-of: 520a98bdf7ae ("phy: qcom: m31-eusb2: clear PLL_EN during init") Signed-off-by: Sasha Levin --- drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c index 0a0d2d9fc8464..95cd3175926d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -25,6 +25,7 @@ #define POR BIT(1) #define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define PHY_ENABLE BIT(0) #define SIDDQ_SEL BIT(1) #define SIDDQ BIT(2) #define FSEL GENMASK(6, 4) @@ -81,6 +82,7 @@ struct m31_eusb2_priv_data { static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1), }; -- 2.53.0