From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC0E614A619 for ; Fri, 1 May 2026 13:19:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777641541; cv=none; b=Ty/cBTrCI5Jx9mOLBAGtj8xm0vQbZq+01AfZFo+uSB/BBxBvFiejNimoZ6B1pE3R3qvFCnl01MqsQqp9pjEG4zaoWyhKg0wapaW9EyfpQX/+GpL4kMxV+V65TGFjodxenVtv3YxQl+eFPa1XxHPQ2Xz0R6q0PIkq1Fb15ENZis8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777641541; c=relaxed/simple; bh=P+bKNktE1A2/VtVciNY9uX+ntikG8SLCGFqqVZfXZUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lomzNIqYCH/BagVE30FN6/aTjmGgHG+UU3BlPlouJXx5FPVtnZuyx5/bd4H+x0efREuujQT4u4CHRyDtibKfm7UzVwmw7MgYG5hF2Az16wpOtAzAv8hJyyTf6deskKymi24tvP7nFNi4hQnSf1KblJcvGxAOq6vFIlxJ9jmDkvk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rDlSP9qe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rDlSP9qe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5F0CC2BCC6; Fri, 1 May 2026 13:19:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777641541; bh=P+bKNktE1A2/VtVciNY9uX+ntikG8SLCGFqqVZfXZUA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rDlSP9qeTuvw7/OemxJLzikSoSwhttCpCOyLq1um98DpyxCYpZk+t8tcvwGHsZ7l6 5OPXnJK16gMJUbbKR+L4jJYYyldwInL1CT7En+gw8PjxZ+Zryg5jXlz+IpuvkMz/Tt OcdR37WPvn5381mzrM6WnwZD0oQK84fIoEa0hKWJJhMdLspYaYmI+oMoS5oNlade4l Gcf2afasX7UEoiEM1otojooDhsjyyS1A90Sm97+s3xx8W76g8Oa2yPRdL+dZYwRf01 uBe1LO2LseUC+5z5WAM6c3BF5KlEF0UcEd7ymzro6vU9Ew9Fhk5oUhV/R6GcYXwfdd N/9hvARDmVnXA== From: Sasha Levin To: stable@vger.kernel.org Cc: Elson Serrao , Konrad Dybcio , Vinod Koul , Sasha Levin Subject: [PATCH 6.18.y 2/2] phy: qcom: m31-eusb2: clear PLL_EN during init Date: Fri, 1 May 2026 09:18:56 -0400 Message-ID: <20260501131857.3242270-2-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260501131857.3242270-1-sashal@kernel.org> References: <2026050131-exfoliate-garter-519b@gregkh> <20260501131857.3242270-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Elson Serrao [ Upstream commit 520a98bdf7ae0130e22d8adced3d69a2e211b41f ] The driver currently sets bit 0 of USB_PHY_CFG1 (PLL_EN) during PHY initialization. According to the M31 EUSB2 PHY hardware documentation, this bit is intended only for test/debug scenarios and does not control mission mode operation. Keeping PLL_EN asserted causes the PHY to draw additional current during USB bus suspend. Clearing this bit results in lower suspend power consumption without affecting normal operation. Update the driver to leave PLL_EN cleared as recommended by the hardware documentation. Fixes: 9c8504861cc4 ("phy: qcom: Add M31 based eUSB2 PHY driver") Cc: stable@vger.kernel.org Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260217201130.2804550-1-elson.serrao@oss.qualcomm.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c index 95cd3175926d5..68f1ba8fec4ad 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -83,7 +83,7 @@ static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1), - M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 0), M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1), }; -- 2.53.0